S3C8245/P8245/C8249/P8249 nRESET and POWER-DOWN
8-1
8nRESET and POWER-DOWN
SYSTEM nRESET
OVERVIEW
During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The
nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3C8245/C8249 into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum
time interval after the power supply comes within tolerance. The minimum required time of a reset operation for
oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the nRESET
pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to
their default hardware values
In summary, the following sequence of events occurs during a reset operation:
—All interrupt is disabled.
—The watchdog function (basic timer) is enabled.
—Ports 0-3 and set to input mode.
—Peripheral control and data register settings are disabled and reset to their default hardware values.
—The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
—When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location
0100H (and 0101H) is fetched and executed.
NORMAL MODE nRESET OPERATION
In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 16-Kbyte on-chip ROM.
(The external interface is not automatically configured).
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing "1010B" to the upper nibble of BTCON.