Samsung C8249, P8245, P8249, S3C8245

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1

12-7

TIMER 1 CONTROL REGISTER (T1CON)

You use the timer 1 control register, T1CON, to

—Select the timer 1 operating mode (interval timer, capture mode, or PWM mode)

—Select the timer 1 input clock frequency

—Clear the timer 1 counter, T1CNTH/L

—Enable the timer 1 overflow interrupt or timer 1 match/capture interrupt

—Clear timer 1 match/capture interrupt pending conditions

T1CON is located in set 1 and Bank 1 at address FBH, and is read/write addressable using Register addressing

mode.

A reset clears T1CON to ‘00H’. This sets timer 1 to normal interval timer mode, selects an input clock frequency of

fxx/1024, and disables all timer 1 interrupts. To disable the counter operation, please set T1CON.7-.5 to 111B. You

can clear the timer 1 counter at any time during normal operation by writing a “1” to T1CON.3.

The timer 1 overflow interrupt (T1OVF) is interrupt level IRQ3 and has the vector address EAH. When a timer 1

overflow interrupt occurs and is serviced interrupt (IRQ3, vector E8H), you must write T1CON.1 to “1”. To generate

the exact time interval, you should write T1CON by the CPU, the pending condition is cleared automatically by

hardware.

To enable the timer 1 match/capture which clear counter and interrupt pending bit. To detect a match/capture or

overflow interrupt pending condition when T1INT or T1OVF is disabled, the application program should poll the

pending bit. When a “1” is detected, a timer 1 match/capture or overflow interrupt is pending.

When her sub-routine has been serviced, the pending condition must be cleared by software by writing a “0” to the

interrupt pending bit.

Timer 1 Control Register (T1CON)

FBH, Set 1, Bank 1, R/W

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Timer 1 match/capture interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 1 overflow interrupt enable:

1 = Enable overflow interrupt

0 = Disable overflow interrupt

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 1 counter (when write)

Timer 1 input clock selection bits:

000 = f

/1024

010 = f

/256

100 = f

/64

110 = f

001 = f

011 = External clock (T1CLK) falling edge

101 = External clock (T1CLK) rising edge

111 = Counter stop

Timer 1 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge, counter running, OVF can occur)

10 = Capture mode (capture on falling edge, counter running, OVF can occur)

11 = PWM mode (OVF & match interrupt can occur)

Figure 12-5. Timer 1 Control Register (T1CON)