S3C8245/P8245/C8249/P8249 ELECTRICAL DATA
19-13
Table 19-11. Main Oscillator Frequency (fOSC1)
(TA = -25 °C to +85 °C, VDD = 1.8 V to 5.5 V)
Oscillator Clock Circuit Test Condition Min Typ Max Unit
Crystal
X
IN
C1 C2
X
OUT
Crystal oscillation frequency 1 – 10 MHz
Ceramic
X
IN
C1 C2
X
OUT
Ceramic oscillation frequency 1 – 10 MHz
External clock
X
IN
X
OUT
XIN input frequency 1 – 10 MHz
RC
X
IN
X
OUT
R
VDD = 5 V 1–2MHz
Table 19-12. Main Oscillator Clock Stabilization Time (tST1)
(TA = -25 °C to +85 °C, VDD = 2.0 V to 5.5 V)
Oscillator Test Condition Min Typ Max Unit
Crystal VDD = 2.0 V to 5.5 V – – 40 ms
Ceramic Stabilization occurs when VDD is equal to the minimum
oscillator voltage range.
––4ms
External clock XIN input high and low level width (tXH, tXL)50 – 500 ns
NOTE:Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a nRESET signal.
The nRESET should therefore be held at low level until the tST1 time has elapsed