S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE
5-11
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in
the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be
written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the
interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority
definitions (see Figure 5-7):
Group A IRQ0, IRQ1
Group B IRQ2, IRQ3, IRQ3
Group C IRQ5, IRQ6, IRQ7
IPR
Group B IPR
Group C
IRQ2
B1
IRQ4
B2
IRQ3
B22B21
IRQ5
C1
IRQ7
C2
IRQ6
C22C21
IPR
Group A
IRQ1
A2
IRQ0
A1
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For
example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would
select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
—IPR.5 controls the relative priorities of group C interrupts.
—Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6,
and 7. IPR.6 defines the subgroup C relationship. IPR. 5 controls the interrupt group C.
—IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.