Main
NOTIFICATION OF REVISIONS
REVISION HISTORY
REVISION DESCRIPTIONS
1. DEVICE TYPE
2. FEATURES
3. ELECTRICAL DATA
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Important Notice
Preface
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Table of Contents
Part I Programming Model
Chapter 1 Product Overview
Chapter 2 Address Spaces
Chapter 3 Addressing Modes
Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set
Part II Hardware Descriptions
Chapter 7 Clock Circuit
Chapter 8 nRESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 8-bit Timer A/B
Chapter 12 16-bit Timer 0/1
Chapter 13 Watch Timer
Chapter 14 LCD Controller/Driver
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Table of Contents
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List of Figures
List of Tables
List of Tables
List of Programming Tips
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List of Register Descriptions
List of Register Descriptions
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List of Instruction Descriptions
1
S3C8-SERIES MICROCONTROLLERS
S3C8245/P8245/C8249/P8249 MICROCONTROLLER
OTP
FEATURES
S3C8245/P8245/C8249/P8249 PRODUCT OVERVIEW
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW S3C8245/P8245/C8249/P8249
1-4
PIN ASSIGNMENT
S3C8245/C8249
Figure 1-2. S3C8245/C8249 Pin Assignments (80-QFP-1420C)
(80-QFP-1420C)
S3C8245/P8245/C8249/P8249 PRODUCT OVERVIEW
1-5
S3C8245/C8249
(80-TQFP-1212)
Figure 1-3. S3C8245/C8249 Pin Assignments (80-TQFP-1212)
PIN DESCRIPTIONS
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PIN CIRCUITS
V
Figure 1-7. Pin Circuit Type D-4 (P0)
In
Figure 1-4. Pin Circuit Type B (nRESET)
Figure 1-8. Pin Circuit Type E-2 (P1)
Figure 1-9. Pin Circuit Type F-10 (P2.0P2.6)
Figure 1-11. Pin Circuit Type H (SEG/COM)
Figure 1-10. Pin Circuit Type F-18 (P2.7/VLDREF)
Figure 1-12. Pin Circuit Type H-4
Figure 1-13. Pin Circuit Type H-14 (P4, P5)
2
PROGRAM MEMORY (ROM)
REGISTER ARCHITECTURE
ADDRESS SPACES S3C8245/P8245/C8249/P8249
~ ~
~
Figure 2-2. Internal Register File Organization
~ ~ ~
~
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S3C8245/P8245/C8249/P8249 ADDRESS SPACES
2-7
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
~ ~
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+
REGISTER ADDRESSING
ADDRESS SPACES S3C8245/P8245/C8249/P8249
Figure 2-9. Register File Addressing
2-12
~ ~ ~~~
+
Figure 2-11. 4-Bit Working Register Addressing
Figure 2-12. 4-Bit Working Register Addressing Example
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S3C8245/P8245/C8249/P8249 ADDRESS SPACES
Figure 2-14. 8-Bit Working Register Addressing Example
2-17
SYSTEM AND USER STACK
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3
REGISTER ADDRESSING MODE (R)
Figure 3-2. Working Register Addressing
Figure 3-1. Register Addressing
INDIRECT REGISTER ADDRESSING MODE (IR)
INDIRECT REGISTER ADDRESSING MODE (Continued)
Figure 3-4. Indirect Register Addressing to Program Memory
~ ~ ~ ~
Figure 3-5. Indirect Working Register Addressing to Register File
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
INDEXED ADDRESSING MODE (X)
~ ~ ~ ~
+
INDEXED ADDRESSING MODE (Continued)
+
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
~ ~
S3C8245/P8245/C8249/P8249 ADDRESSING MODES
+
3-9
INDEXED ADDRESSING MODE (Concluded)
Figure 3-9. Indexed Addressing to Program or Data Memory
~ ~
DIRECT ADDRESS MODE (DA)
DIRECT ADDRESS MODE (Continued)
Figure 3-11. Direct Addressing for Call and Jump Instructions
INDIRECT ADDRESS MODE (IA)
RELATIVE ADDRESS MODE (RA)
+
IMMEDIATE MODE (IM)
4
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CONTROL REGISTERS S3C8245/P8245/C8249/P8249
4-4
FLAGS - System Flags Register
D5H
Figure 4-1. Register Description Format
Set 1
ADCON A/D Converter Control Register F7H Set 1, Bank 1
BTCON
CLKCON
EMT
FLAGS
IMR
I NTPND
IPH
IPL
IPR
IRQ
LCON
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LMOD
OSCCON
P0CONH Port 0 Control Register (High Byte) E0H Set 1,Bank 0
P0CONL Port 0 Control Register (Low Byte) E1H Set 1, Bank 0
P0INT Port 0 Interrupt Control Register E2H Set 1, Bank 0
P0PND Port 0 Interrupt Pending Register E3H Set 1, Bank 0
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P1CONH Port 1 Control Register (High Byte) E4HSet 1, Bank 0
P1CONL Port 1 Control Register (Low Byte) E5HSet 1, Bank 0
P1PUP Port 1 Pull-up Control Register F5H Set 1, Bank 0
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P2CONH Port 2 Control Register (High Byte)E6HSet 1, Bank 0
P2CONL Port 2 Control Register (Low Byte)E7HSet 1, Bank 0
P3CONH Port 3 Control Register (High Byte)E8HSet 1, Bank 0
P3CONL Port 3 Control Register (Low Byte)E9HSet 1, Bank 0
P4CONH Port 4 Control Register (High Byte)ECH Set 1, Bank 1
P4CONL Port 4 Control Register (Low Byte)EDHSet 1, Bank 1
P5CONH
P5CONL Port 5 Control Register (Low Byte)EFHSet 1, Bank 1
PP
RP0
RP1
SIOCON
SPH
SPL
STPCON
SYM
T0CON
T1CON
T A CON
T B CON
VLDCON
WT CON
5
INTERRUPT STRUCTURE S3C8245/P8245/C8249/P8249
5-2
Figure 5-1. S3C8-Series Interrupt Types
S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE
5-3
Figure 5-2. S3C8245/C8249 Interrupt Structure
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INTERRUPT STRUCTURE S3C8245/P8245/C8249/P8249
Figure 5-8. Interrupt Priority Register (IPR)
5-12
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6
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ADC
ADD Add
AND Logical AND
BAND Bit AND
BCP Bit Compare
BITC Bit Complement
BITR
BITS
BOR
BTJRF Bit Test, Jump Relative on False
BTJRT
BXOR
CALL
CCF
CLR
COM
CP
CPIJE
CPIJNE
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DA
DEC
DECW
DI
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
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LD
LDB
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LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
MULT
NEXT
NOP
OR
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR
7
CLOCK CIRCUIT S3C8245/P8245/C8249/P8249
7-2
Figure 7-3. System Clock Circuit Diagram
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CLOCK CIRCUIT S3C8245/P8245/C8249/P8249
7-4
Figure 7-5. Oscillator Control Register (OSCCON)
Figure 7-6. STOP Control Register (STPCON)
8
SYSTEM nRESET
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POWER-DOWN MODES
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9
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I/O PORTS S3C8245/P8245/C8249/P8249
9-4
Figure 9-1. Port 0 High-Byte Control Register (P0CONH)
Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)
9-5
Figure 9-3. Port 0 Interrupt Control Register (P0INT)
Figure 9-4. Port 0 Interrupt Pending Register (P0PND)
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9-7
Figure 9-6. Port 1 Low-Byte Control Register (P1CONL)
Figure 9-7. Port 1 Pull-up Control Register (P1PUP)
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Figure 9-9. Port 2 Low-Byte Control Register (P2CONL)
9-9
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Figure 9-11. Port 3 Low-Byte Control Register (P3CONL)
9-11
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Figure 9-13. Port 4 Low-Byte Control Register (P4CONL)
9-13
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Figure 9-15. Port 5 Low-Byte Control Register (P5CONL)
9-15
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10
BASIC TIMER S3C8245/P8245/C8249/P8249
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
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BASIC TIMER S3C8245/P8245/C8249/P8249
Figure 10-2. Basic Timer Block Diagram
10-4
11
8-BIT TIMER A
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Figure 11-2. Timer A Functional Block Diagram
8-BIT TIMER B
Figure 11-3. Timer B Functional Block Diagram
8-BIT TIMER A/B S3C8245/P8245/C8249/P8249
11-6
Figure 11-4. Timer B Control Register (TBCON)
Figure 11-5. Timer B Data Registers (TBDATAH/L)
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Figure 11-6. Timer B Output Flip-Flop Waveforms in Repeat Mode
F
F PROGRAMMING TIP To generate a one pulse signal through P3.0
12
16-BIT TIMER 0
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Figure 12-2. Timer 0 Functional Block Diagram
16-BIT TIMER 0/1 S3C8245/P8245/C8249/P8249
12-4
Figure 12-3. Timer 0 Counter Register (T0CNTH/L)
Figure 12-4. Timer 0 Data Register (T0DATAH/L)
16-BIT TIMER 1
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16-BIT TIMER 0/1 S3C8245/P8245/C8249/P8249
Figure 12-6. Timer 1 Functional Block Diagram
12-8
S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1
12-9
Figure 12-7. Timer 1 Control Register (T1CNTH/L)
Figure 12-8. Timer 1 Data Register (T1DATAH/L)
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13
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S3C8245/P8245/C8249/P8249 WATCH TIMER
13-3
WATCH TIMER CIRCUIT DIAGRAM
Figure 13-1. Watch Timer Circuit Diagram
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14
LCD CIRCUIT DIAGRAM
Figure 14-2. LCD Circuit Diagram
Figure 14-3. LCD Display Data RAM Organization
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LCD CONTROLLER/DRIVER S3C8245/P8245/C8249/P8249
14-8
Figure 14-5. Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode
Figure 14-6. Select/No-Select Bias Signals in 1/3 Duty, 1/3 Bias Display Mode
Figure 14-7. LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode
Figure 14-8. LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode
S3C8245/P8245/C8249/P8249 LCD CONTROLLER/DRIVER
Figure 14-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode
14-11
LCD CONTROLLER/DRIVER S3C8245/P8245/C8249/P8249
14-12
Figure 14-10. Voltage Dividing Resistor Circuit Diagram
15
FUNCTION DESCRIPTION
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Figure 15-3. A/D Converter Functional Block Diagram
S3C8245/P8245/C8249/P8249 A/D CONVERTER
Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
15-5
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16
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S3C8245/P8245/C8249/P8249 SERIAL I/O INTERFACE
16-3
SIO Pre-scaler Register (SIOPS) F2H, Set 1, Bank 0 R/W .7 .6 .5 .4 .3 .2 .1 .0MSB LSB Baud rate = (f
Figure 16-3. SIO Functional Block Diagram
/4)/(SIOPS + 1)
Figure 16-2. SIO Pre-scale Registers (SIOPS)
SERIAL I/O INTERFACE S3C8245/P8245/C8249/P8249
16-4
SERIAL I/O TIMING DIAGRAM
Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
17
FUNCTION DESCRIPTION
Figure 17-1. Voltage Booster Block Diagram
Figure 17-2. Pin Connection Example
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Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts
Figure 19-5. Stop Mode (Sub) Release Timing Initiated by Interrupts
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20
The S3C8245/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package.
Figure 20-1. Package Dimensions (80-QFP-1420C)
80-QFP-1420C
80-TQFP-1212
Figure 20-2. Package Dimensions (80-TQFP-1212)
21
S3P8245/P8249 OTP S3C8245/P8245/C8249/P8249
21-2
S3P8245/P8249
80-QFP (Top View)
Figure 21-1. S3P8245/P8249 Pin Assignments (80-QFP) Package
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22
Figure 22-1. SMDS Product Configuration (SMDS2+)
TB8245/8249
Figure 22-2. TB8245/8249 Target Board Configuration
+
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DEVELOPMENT TOOLS S3C8245/P8245/C8249/P8249
40-Pin DIP Connector
22-6
40-Pin DIP Connector
Figure 22-3. 40-Pin Connectors (J101, J102) for TB8245/8249
Target Board 40-Pin DIP Connector
Figure 22-4. S3E8240 Cables for 80-QFP Package
Target System J102 41 42
J101 1 2
