Samsung C8249, P8245, P8249, S3C8245 Figure 11-4. Timer B Control Register (TBCON), Figure 11-5. Timer B Data Registers (TBDATAH/L)

8-BIT TIMER A/B S3C8245/P8245/C8249/P8249
11-6
Timer B Control Register (TBCON)
ECH, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Timer B mode selection bit:
0 = One-shot mode
1 = Repeating mode
Timer B output flip-flop control bit:
0 = TBOF is low
1 = TBOF is high
Timer B start/stop bit:
0 = Stop timer B
1 = Start timer B
Timer B interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer B input clock selection bits:
00 = fxx
01 = fxx/2
10 = fxx/4
11 = fxx/8
Timer B interrupt time selection bits:
00 = Elapsed time for low data value
01 = Elapsed time for high data value
10 = Elapsed time for low and high data values
11 = Invalid setting
Figure 11-4. Timer B Control Register (TBCON)
Timer B Data Register, High Byte (TBDATAH)
FAH, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFh
Timer B Data Register, Low-Byte (TBDATAL)
EBH, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFh
Figure 11-5. Timer B Data Registers (TBDATAH/L)