Sonic Alert msm83c154s External interrupt signal 0 and 1 trigger detection, BUS Tcon Reset

INTERNAL SPECIFICATIONS

4.7.4.3 External interrupt signal 0 and 1 trigger detection

When bit 0 (IT0) in the timer Control register (TCON 88H) is “1”, external interrupt 0 is edge- activated. And when bit 2 (IT1) is “1”, external interrupt 1 is also edge-activated. With the external interrupt signals in trigger-detect mode, external interrupts 0 and 1 are trigger- detected by the equivalent circuit shown in Figure 4-48. When the level of the external interrupt pin is “0” at S5 timing, the level is latched at the first stage and the latched Q output becomes “1”. The external interrupt signal stored in the first stage latch is transferred to the second stage latch and is subject to digital differentiation until the S3 timing signal. The RS- F/F in the next stage is set by the differentiated output signal.

The external interrupt signal applied to the RS-F/F is synchronized with the M2·S3 timing signal to be applied as a trigger for the external interrupt flag in the timer control register (TCON). The RS-F/F is subsequently reset at M2·S4 and waits for the next interrupt. Note that the next interrupt signal is invalid until the first stage latch detects level “1” after detecting level “0”.

The cycle width of the respective “0” and “1” levels of the external interrupt signal applied to the external interrupt pin in this case must be at least 12 times (12T) the XTAL1·2 oscillator clock cycle time T.

INT0 or INT1

S5

1

S3

0

12T 12T 12T

S4

S3

M2

DQ

L

D

LQ

BUS

W TCON

RESET

IE0 or 1

SQ

D L R

Figure 4-48 lnterrupt edge detect equivalent circuit for IT bit “1”

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