Sonic Alert msm80154s Instruction Register IR and Instruction Decoder PLA, Air, PLA Wair, Pla Wir

MSM80C154S/83C154S/85C154HVS

2.7 Instruction Register (IR) and Instruction Decoder (PLA)

MSM80C154S/MSM83C154S operations are based on an instruction code address method. Hence, in addition to the instruction code instruction register (IR) and instruction decoder (PLA), these devices also include an instruction register (AIR) and register manipulation decoder (PLA) for data addresses and bit addresses.

Operation codes are passed to the IR, and data and bit addresses are passed to the AIR. CPU control signals are formed at the respective PLA for each instruction register, thereby activating the CPU. The block diagram is outlined in Figure 2-21.

			Timing
		Matrix	AND
Data bus	AIR	Decoder
		PLA
WAIR
			Timing
		Matrix	AND
Data bus	IR	Decoder
		PLA
WIR

Control signals

Control signals

Figure 2-21 lR and PLA block diagram

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