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Sonic Alert msm80154s, msm83c154s, msm85c154hvs 294, 42. JB bit address, code address (Jump if bit is set)

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MSM80C154S/83C154S/85C154HVS

29442. JB bit address, code address (Jump if bit is set)

00100000

Instruction code

Bit address

Relative offset

Operations

Number of bytes

Number of cycles

Flags

(PSW)

Description

: Byte 1

R7R6R5R4R3R2R1R0

Byte 3

(PC)←(PC)+3

IF (bit address)=1

THEN

(PC)←(PC)+relative offset

C AC F0 RS1 RS0 OV F1 P

Control is shifted to a relative jump address if the specified bit

address content is 1.

Control is shifted to the next address following this instruction if

the content is 0.

b7b6b5b4b3b2b1b0

Byte 2

Contents

Main Page CONTENTS 1. INTRODUCTION 2. SYSTEM CONFIGURATION 3. CONTROL 4. INTERNAL SPECIFICATIONS Page 5. INPUT/OUTPUT PORTS 6. ELECTRICAL CHARACTERISTICS 7. DESCRIPTION OF INSTRUCTIONS Page Page 1. INTRODUCTION 1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline Page 1.2 MSM80C154S/MSM83C154S Features Page 1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS Page Page Page 2. SYSTEM CONFIGURATION 2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols 2.2 MSM80C154S/MSM83C154S pin layouts Figure 2-2 MSM80C154S/MSM83C154S pin layout (top view) Applicable Packages 2.2.1 MSM80C154S/MSM83C154S external dimensions Page 2.2.2 MSM85C154HVS pin layout and external dimensions 2.3 MSM80C154S Block Diagram 2.4 MSM83C154S Block Diagram 2.5 MSM85C154HVS Block Diagram 2.6 Timing and Control Figure 2-9 MSM80C154S/MSM83C154S fundamental timing Page 24 2.6.3 MSM80C154S fundamental operation time charts (2) MOVX A, @Rr (1) External program memory read cycle timing chart 25 (3) MOVX @Rr, A (4) MOVX A, @DPTR 26 (5) MOVX @DPTR, A (6) MOV direct, PORT [0, 1, 2, 3] execution 27 2.6.4 MSM83C154S fundamental operation time charts (2) MOVX @Rr, A (1) MOVX A, @Rr 28 (3) MOVX A, @DPTR (4) MOVX @DPTR, A 29 (5) MOV direct, PORT [0, 1, 2, 3] execution 2.7 Instruction Register (IR) and Instruction Decoder (PLA) 2.8 Arithmetic Operation Section 2.9 Program Counter 2.10 Program Memory and External Data Memory Page Page Page Figure 2-27 DPTR external data memory access timing Page Page Figure 2-29 Register R0/R1 external data memory access timing Page Page 3. CONTROL 3.1 Oscillators: XTAL1 XTAL2 44 * Supply of 50% duty clock 3.2 CPU Resetting Figure 3-5 Reset execution time chart (internal ROM mode) CONTROL Figure 3-6 Reset execution time chart (external ROM mode) 47 Figure 3-7 Reset release time chart (internal ROM mode) CONTROL Figure 3-8 Reset release time chart (external ROM mode) 49 Page Page 3.3 EA (CPU Memory Separate) Page Page 4. INTERNAL SPECIFICATIONS 4.1 Internal Data Memory (RAM) and Special Function Registers Figure 4-1 Data memory and special function register layout 4.2 Internal Data Memory (RAM) Figure 4-2 RAM layout diagram 59 Page 4.3 lnternal Data Memory (RAM) Operating Procedures Page Page Page 4.4 Special Function Registers (TCON, SCON,.... ACC, B) Table 4-6 List of special function registers 67 4.4.2 Special function registers 4.4.2.1 Timer mode register (TMOD) 68 4.4.2.2 Power control register (PCON) 69 4.4.2.3 Timer control register (TCON) 70 4.4.2.4 Serial port control register (SCON) 71 4.4.2.5 Interrupt enable register (IE) 72 4.4.2.6 Interrupt priority register (IP) 73 4.4.2.7 Program status word register (PSW) 74 4.4.2.8 I/O control register (IOCON) 75 4.4.2.9 Timer 2 control register (T2CON) 4.5 Timer/Counters 0, 1 and 2 4.5.1 Outline Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1 Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 4.6 Serial Port Page Page Table 4-15 SCON Page Page Page Page Page Figure 4-29 Serial port (mode 0) timing chart Page Page Page Page Page Figure 4-32 Serial port (mode 1) timing chart Page Page Page Figure 4-34 Serial port (mode 2) timing chart Page Page Page Page Figure 4-36 Serial port (mode 3) timing chart Page Page Page Page Page 4.7 Interrupt Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 4.8 CPU Power Down Figure 4-53 ldle mode equivalent circuit Table 4-23 CPU pin details in idle mode Figure 4-54 Idle mode setting time chart (internal ROM mode) Figure 4-55 Idle mode setting time chart (external ROM mode) Page Page Page Page Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD) Figure 4-60 Soft power down mode setting time chart (internal ROM mode) Figure 4-61 Soft power down mode setting time chart (external ROM mode) Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD) Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode) Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode) Page Page Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD) Figure 4-65 Hard power down mode setting time chart (internal ROM mode) Figure 4-66 Hard power down mode setting time chart (external ROM mode) Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD) Figure 4-67 Hard power down mode setting and I/O floating time chart (internal ROM mode) Figure 4-68 Hard power down mode setting andl/Of loating time chart (external ROM mode) 4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) Figure 4-69 Restart from idle mode by reset (internal ROM mode) Figure 4-70 Restart from idle mode by reset (external ROM mode) Figure 4-71 Restart from soft power mode by reset (internal ROM mode) Figure 4-72 Restart from soft power mode by reset (external ROM mode) Figure 4-73 Restart from hard power down mode by reset (internal ROM mode) Figure 4-74 Restart from hard power down mode by reset (external ROM mode) Page Page Figure 4-76 Restart from idle mode by interrupt INT0 or 1 (internal ROM mode) Figure 4-77 Restart from idle mode by interrupt INT0 or 1 (external ROM mode) Figure 4-78 Restart from soft power down mode by Interrupt INT0 or 1 (internal ROM mode) Figure 4-79 Restart from soft power down mode by interrupt INT0 or 1 (external ROM mode) Page Figure 4-81 Restart from idle mode by INT0 or 1 (internal ROM mode) Figure 4-82 Restart from idle mode by INT0 or 1 (external ROM mode) Figure 4-83 Restart from soft power down mode by INT0 or 1 (internal ROM mode) Figure 4-84 Restart from soft power down mode by INT0 or 1 (external ROM mode) 4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode Figure 4-85-2/2 MSM80C154S/83C154S battery back up with hard power down mode Page Page 5. INPUT/OUTPUT PORTS 5.1 Outline 5.2 Port 0 Page Page 5.3 Port 1 Page Page Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart Page Page 5.4 Port 2 Page 5.5 Port 3 Page 5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD) Figure 5-11 Control circuit for ports 0, 1, 2, 3 by lOCON 5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2, and 3 5.8 100 kohm Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1, 2, and 3 5.9 Precautions When Driving External Transistors by Ouasi-bidirectional Port Output Signals Page 210 5.10 Port Output Timing Figure 5-15 One machine cycle instruction port output time chart 1) One machine cycle instruction output timing 211 2) Two machine cycle instruction output timing Figure 5-16 Two machine cycle instruction port output time chart 5.11 Port Data Manipulating Instructions Page Page Page 216 6. ELECTRICAL CHARACTERISTICS Supply Voltage VCC (V) 6.1 Absolute Maximum Ratings 6.2 Operational Ranges t ( m s) f 6.3 DC Characteristics 1 (VCC=4.0 to 6.0V,VSS=0V, Ta=40C to +85C) Page 219 DC Characteristics 2 Maximum power supply current idle mode ICC (mA) Maximum power supply current normal operation ICC (mA) 220 Measuring circuits 221 6.4 External Program Memory Access AC Characteristics *1 The variable check is from 0 to 24 MHz when the external check is used. Page 223 6.5 External Data Memory Access AC Characteristics *1 The variable check is from 0 to 24 MHz when the external check is used. *2 For 2.2VCC<4 V Page 225 6.6 Serial Port (I/O Extension Mode) AC Characteristics VCC=2.2 to.0V, VSS=0V, Ta=40C to 85C Page 227 6.7 AC Characteristics Measuring Conditions 1. Input/output signal 2. Floating 6.8 XTAL1 External Clock Input Waveform Conditions Page Page 7. DESCRIPTION OF INSTRUCTIONS 7.1 Outline 7.2 Description of Instruction Symbols 233 7.3 List of Instructions MSM80C154S/MSM83C154S instruction table 7.4 Simplified Description of Instructions 234 Note that data address is represented as direct address in this description. Page Page Page Page Page Page Page Page Page Page Page 246 7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions 247 2. ADD A, #data (Add immediate data) 248 3. ADD A, @Rr (Add indirect address) 249 4. ADD A, Rr (Add register) 250 5. ADD A, data address (Add memory) 251 6. ADDC A, #data (Add carry plus immediate data to accumulator) 252 7. ADDC A, @Rr (Add carry plus indirect address to accumulator) 253 8. ADD A, Rr (Add carry plus register to accumulator) 254 9. ADDC A, data address (Add carry plus memory to accumulator) 255 10. AJMP code address (Absolute jump within 2K byte page) 256 11. ANL A, #data (Logical AND immediate data to accumulator) 257 12. ANL A, @Rr (Logical AND indirect address to accumulator) 258 13. ANL A, Rr (Logical AND register to accumulator) 259 14. ANL A, data address (Logical AND memory to accumulator) 260 15. ANL C, bit address (Logical AND bit to carry flag) 261 16. ANL C,/bit address (Logical AND complement bit to carry flag) 262 17. ANL data address, #data (Logical AND immediate data to memory) 263 18. ANL data address, A (Logical AND accumulator to memory) 264 19. CJNE @Rr, #data, code address (Compare indirect address to immediate data, jump if not equal) Page 266 20. CJNE A, #data, code address (Compare immediate data to accumulator, jump if not equal) Page 268 21. CJNE A, data address, code address (Compare memory to accumulator, jump if not equal) Page 270 22. CJNE Rr, #data, code address (Compare immediate data to register, jump if not equal) Page 272 23. CLR A (Clear accumulator) 273 24. CLR C (Clear carry flag) 274 25. CLR bit address (Clear bit) 275 26. CPL A (Complement accumulator) 276 27. CPL C (Complement carry flag) 277 28. CPL bit address (Complement bit) 278 29. DA A (Decimal adjust accumulator) } Page 280 30. DEC @Rr (Decrement indirect address) 281 31. DEC A (Decrement accumulator) 282 32. DEC Rr (Decrement register) 283 33. DEC data address (Decrement memory) 284 34. DIV AB (Divide accumulator by B) 285 35. DJNZ Rr, code address (Decrement register, and jump if not zero) Page 287 36. DJNZ data address, code address (Decrement memory, and jump if not zero) Page 289 37. INC @Rr (Increment indirect address) 290 38. INC A (Increment accumulator) 291 39. INC DPTR (Increment data pointer) 292 40. INC Rr (Increment register) 293 41. INC data address (Increment memory) 294 42. JB bit address, code address (Jump if bit is set) Page 296 43. JBC bit address, code address (Jump and clear if bit is set) Page 298 44. JC code address (Jump if carry is set) Page 300 45. JMP @A + DPTR (Jump to sum of accumulator and data pointer) 301 46. JNB bit address, code address (Jump if bit is not set) Page 303 47. JNC code address (Jump if carry is not set) Page 305 48. JNZ code address (Jump if accumulator is not 0) Page 307 49. JZ code address (Jump if accumulator is not 0) Page 309 50. LCALL code address (Long call) 310 51. LJMP code address (Long jump) 311 52. MOV @Rr, #data (Move immediate data to indirect address) 312 53. MOV @Rr, A (Move accumulator to indirect address) 313 54. MOV @Rr, data address (Move memory to indirect address) 314 55. MOV A, #data (Move immediate data to accumulator) 315 56. MOV A, @Rr (Move indirect address to accumulator) 316 57. MOV A, Rr (Move register to accumulator) 317 58. MOV A, data address (Move memory to accumulator) 318 59. MOV C, bit address (Move bit to carry flag) 319 60. MOV DPTR, #data (Move immediate data to data pointer) 320 61. MOV Rr, #data (Move immediate data to register) 321 62. MOV Rr, A (Move accumulator to register) 322 63. MOV Rr, data address (Move memory to register) 323 64. MOV bit address, C (Move carry flag to bit) 324 65. MOV data address, #data (Move immediate data to memory) 325 66. MOV data address, @Rr (Move indirect address to memory) 326 67. MOV data address, A (Move accumulator to memory) 327 68. MOV data address, Rr (Move register to memory) 328 69. MOV data address 1, data address 2 (Move memory to memory) 329 70. MOVC A, @A + DPTR (Move code memory offset from data pointer to accumulator) 330 71. MOVC A, @A + PC (Move code memory offset from program counter to accumulator) 331 72. MOVX @DPTR, A (Move accumulator to external memory addressed by data pointer) 332 73. MOVX @Rr, A (Move accumulator to external memory addressed by register) 333 74. MOVX A, @DPTR (Move external memory addressed by data pointer to accumulator) 334 75. MOVX A, @Rr (Move external memory addressed by register to accumulator) 335 76. MUL AB (Multiply accumulator by B) 336 77. NOP (No operation) 337 78. ORL A, #data (Logical OR immediate data to accumulator) 338 79. ORL A, @Rr (Logical OR indirect address to accumulator) 339 80. ORL A, Rr (Logical OR register to accumulator) 340 81. ORL A, data address (Logical OR memory to accumulator) 341 82. ORL C, bit address (Logical OR bit to carry flag) 342 83. ORL C,/bit address (Logical OR complement of bit to carry flag) 343 84. ORL data address, #data (Logical OR immediate data to memory) 344 85. ORL data address, A (Logical OR accumulator to memory) 345 86. POP data address (Pop stack to memory) 346 87. PUSH data address (Push memory onto stack) 347 88. RET (Return from subroutine, non interrupt) 348 89. RETI (Return from interrupt routine) 349 90. RL A (Rotate accumulator left) 350 91. RLC A (Rotate accumulator and carry flag left) 351 92. RR A (Rotate accumulator right) 352 93. RRC A (Rotate accumulator and carry flag right) 353 94. SETB C (Set carry flag) 354 95. SETB bit address (Set bit) 355 96. SJMP code address (Short jump) Page 357 97. SUBB A, #data (Substract immediate data from accumulator with borrow) 358 98. SUBB A, @Rr (Substract indirect address from accumulator with borrow) 359 99. SUBB A, Rr (Substract register from accumulator with borrow) 360 100. SUBB A, data address (Substract memory from accumulator with borrow) 361 101. SWAP A (Exchange nibble in accumulator) 362 102. XCH A, @Rr (Exchange indirect address with accumulator) 363 103. XCH A, Rr (Exchange register with accumulator) 364 104. XCH A, data address (Exchange memory with accumulator) 365 105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator) 366 106. XRL A, #data (Logical exclusive OR immediate data to accumulator) 367 107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator) 368 108. XRL A, Rr (Logical exclusive OR register to accumulator) 369 109. XRL A, data address (Logical exclusive OR memory to accumulator) 370 110. XRL data address, #data (Logical exclusive OR immediate data to memory) 371 111. XRL data address, A (Logical exclusive OR accumulator to memory)