Sonic Alert msm80154s Reset Schmitt trigger circuit CPU internal status by reset, 2.5.2, 2.5.3

3. CONTROL

3.1	Oscillators [XTAL1 .2]			43
3.2	CPU Resetting			45
3.2.1		Outline		45
3.2.2 Reset Schmitt trigger circuit				50
3.2.3 CPU internal status by reset				51
3.3	EA(CPU Memory Separate)			52
3.3.1		Outline		52
		(1)	Internal ROM mode	52
		(2)	External ROM mode	52

4. INTERNAL SPECIFICATIONS

4.1 Internal Data Memory (RAM) and Special Function Registers			55
4.1.1 Outline		..........................................................................................................	55
4.2 Internal Data Memory (RAM)			57
4.2.1 Internal data memory (RAM)			57
4.2.2 Internal data memory registers R0 thru R7			59
4.2.3	Stack	..........................................................................................................	60
4.3 Internal Data Memory (RAM) Operating Procedures			61
4.3.1 Internal data memory indirect addressing			61
4.3.2 Internal data memory register R0 thru R7 designation			62
4.3.3 Internal data memory 1-bit data designation			63
4.4 Special Function Registers(TCON, SCON,...ACC, B)			65
4.4.1	Outline		65
4.4.2	Special function registers		67
4.4.2.1 Timer mode register (TMOD)			67
4.4.2.2 Power control register (PCON)			68
4.4.2.3 Timer control register (TCON)			69
4.4.2.4 Serial port control register (SCON)			70
4.4.2.5 Interrupt enable register (IE)			71
4.4.2.6 Interrupt priority register (IP)			72
4.4.2.7 Program status word register (PSW)			73
4.4.2.8 I/O control register (IOCON)			74
4.4.2.9 Timer 2 control register (T2CON)			75
4.5 Timer/Counters 0, 1, and 2			76
4.5.1	Outline		76
4.5.2 Timer/counters 0 and 1			76
4.5.2.1 Outline			76
4.5.2.2 Timer/counter 0 and 1 counting control			76
4.5.2.3 Timer/counter 0 and 1 count clock designation			78
4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1			79
4.5.2.4 Counting control of timer/counters 0 and 1 by INT pin			80
4.5.2.5 Timer/counters 0/1 timer modes			82
4.5.2.5.1		Outline	82
4.5.2.5.2		Mode 0	82
4.5.2.5.3		Mode 1	84
4.5.2.5.4		Mode 2	86
4.5.2.5.5		Mode 3	88
4.5.2.5.6		32-bit timer mode	89