134, Clrea | Sonic Alert msm83c154s, msm80154s, msm85c154hvs

MSM80C154S/83C154S/85C154HVS

4.7.3.2 Interrupt routine flow when priority circuit is stopped

When bit 7 (PCT) of the priority register (IP 0B8H) is set to “1”, all interrupt control is transferred to the interrupt enable register (IE 0A8H). When this mode is set, the interrupt disable instruction (CLR EA) must always be placed at the beginning of the interrupt routine to prevent any other interrupt from being generated. If another interrupt routine have to be generated during the processing of an interrupt routine, set the desired interrupt enable bit in the interrupt enable register (IE 0A8H) to commence the new interrupt routine. Multi-level interrupt processing can thus be achieved by control of the interrupt enable register. The flow of this interrupt routine is shown in Figure 4-46.

Main routine

M

CLREA

CLREA

CLREA

CLREA

EA

EA

EA

EA

Generation	Generation	Generation	Generation
of interrput	of interrput	of interrput	of interrput

EA

RETI

M

Main routine

RETI

RETI

Interrput routine

RETI

Figure 4-46 lnterrupt routine flow chart when priority circuit is stopped

134

Image 141

Sonic Alert msm83c154s, msm80154s, msm85c154hvs user manual 134, Clrea

Contents

MSM80C154S MSM83C154S Page Contents 2.5.2 Reset Schmitt trigger circuit CPU internal status by reset2.5.3 2.5.4 3.4.2 T2EXtimer/counter 2 external flag input detector Power down mode3.1 Special function registers for serial port 101 2.1 129 Multi-processor systems 128140 142 207 KW Pull-Up Resistance Setting for Quasi-bidirectional Input208 210 Introduction Page MSM80C154S/MSM83C154S/MSM85C154HVS Outline Introduction MSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154SRS/MSM83C154SRS MSM80C154S/MSM83C154S pin layouts MSM80C154S/MSM83C154S pin layout top view Applicable Packages MSM80C154S/MSM83C154S external dimensions 1 MSM80C154S/MSM83C154S external dimensions MSM80C154STS/MSM83C154STS MSM85C154HVS pin layout and external dimensions 2 MSM85C154HVS pin layout and external dimensions TIMER/COUNTER 0&1 Interrupt Serial IO SignalSpecial Function Register Address DPL PLA Register Address ROM SpecialSense AMP TH1 TL1 TH0 TL0 Tmod Tcon T2CON TL2 TH2 AMP ACC TR2 TR1 Signal DPHAddress Decoder TH1 TL1 TH0 TL0 Outline of MSM80C154S/MSM83C154S timing Timing and Control 9MSM80C154S/MSM83C154S Timing Major synchronizing signals External program memory read cycle timing chart Movx A, @RrXTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT 13 MSM80C154S Movx A, @DPTR execution 12 MSM80C154S Movx @Rr, a execution MOV direct, Port 0, 1, 2, 3 execution XTAL1 ALE PsenPIN Data CPU Data PIN Data Stable Sampled 16 MSM83C154S Movx A, @Rr execution 4 MSM83C154S fundamental operation time charts 19 MSM83C154S Movx @DPTR, a execution 18 MSM83C154S Movx A, @DPTR execution 20 MSM83C154S MOV direct, PORT0, 1, 2, 3 execution PIN Data PIN Data Stable CPU Data Sampled AIR Instruction Register IR and Instruction Decoder PLAPLA Wair PLA WIR PSW0D0H CY AC F0 RS1 RS0 OV F1 P Arithmetic Operation Section CPU Internal Data BUS Program Counter 24 MSM80C154S/MSM83C154S program area Program Memory and External Data Memory ALE Latch System Configuration Dptr XTAL1 ALE Psen Page By register R0 or R1 MSM80C154S/MSM83C154S Data Control Page Oscillators XTAL1 XTAL2 Crystal resonator connection diagram Clock XTAL2 Supply of 50% duty clock CPU Resetting CPU Reset ControlOutline 5Resetexecution ROM mode Chart Chart XTAL1 Psen ALE Reset Schmitt trigger gate detector time chart MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuit CPU internal status by reset Denotes direct resetting even if XTAL1·2 has stoppedMSM80C154S/MSM83C154S reset internal status EA CPU Memory Separate Internal Specifications Page Internal Data Memory RAM and Special Function Registers Internal Specifications Data memory and special function register layout Internal data memory RAM Internal Data Memory RAM RAM layout diagram Program status word PSW Internal data memory registers R0 thru R7RS0 User Data RAM Stack storage layout MSM80C154S/83C154S/85C154HVS StackPC5 PC1 Internal data memory indirect addressing Lnternal Data Memory RAM Operating Procedures DEC Rr bit arrangement Register designation table CLR bit address bit arrangement Internal data memory 1-bit data designation Addressing combination table Bit designation table2AH 2BH 2EH Special Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon MSB LSB Scon SCON.6 SM1 SM0 ModeSM0 SM1 SM2 REN TB8 RB8 SCON.0 MSB LSB Interrupt enable register IEET2 ET1 EX1 ET0 EX0 ET2 MSM80C154S/83C154S/85C154HVS Interrupt priority register IP PCT PT2 PT1 PX1 PT0 PX0PCT Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon TF2 EXF2 Timer 2 control register T2CONEXEN2 TF2 Timer/counters 0 and 1 4.5.2.1 Outline Timer/Counters 0, 1 and 2 4.5.1 OutlineTimer/counter 0 and 1 counting control Timer control register Tcon 88H Overall clock input control Circuit for timer/counters 0 Timer mode register Tmod 89H External clock detector circuit for timer/counters 0 TimerPD & HPD Detector circuit operational time chart Counting control of timer/counters 0 and 1 by INT pin Timer Clock Timer Gate TR0 INT0 RUN Stop TR1 INT1Detector 11 Timer mode register Tmod 89H Timer CounterMode Detector TF0 TL0 TH0 5BITS 8BITS T0 PIN Detector Port TR0 Gate INT0 PIN DataT1 PIN Detector Port TR1 Gate INT1 PIN Data Latch Detector TF1 TL1 TH1 5BITS 8BITS O Clock MSM80C154S/83C154S/85C154HVS Mode TH0 8BITS Detector TF0Latch Detector TF1 TH1 8BITS O Clock MSM80C154S/83C154S/85C154HVS Mode 8BITS TR0 Gate T0 PIN Detector Port TF0INT0 PIN 8BITS Data Reload Data Xtal Latch Xtal Detector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN DataTL0 8BITS Detector TF1 TH0 C 8BITS T0 PIN Detector 2.5.6 32-bit timer modeIocon 0F8H Serr IZC 19 T0, T1 external clock detector circuit Timer Reset Internal Specifications Mode 1 or 3 has been set 12 Timer 2 control register T2CON 0C8HBit is 0, and valid when Timer/counter 2 operation modes Must be reset to 0 by software3.3.1 16-bit auto reload mode To 0 by software TR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 Interrupt 3.3.2 16-bit capture modeRCLK=0 TCLK=0 TL2 TH2 BIT 21 Timer/counter 2 16-bit capture mode circuit 3.3.3 16-bit baud rate generator mode Baud 3.4.2 T2EX timer/counter 2 external flag input detector Reset Timer Counter ClockReset Timer Counter T2EX Detector PD & HPD O Clock Timer/counter detector circuit Serial Port 100 RX Control Input Shift RegisterSbuf R Internal Specifications 15 Scon 102 Tclk Sbuf serial port buffer registerRclk 16 Serial port operation modes MSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 baud rate Mode 0 transmit operationMode 0 receive operation 107 Port mode Serial port mode Timing chart108 109 Mode 1 baud rate MSM80C154S/83C154S/85C154HVS Mode Outline Mode 1 receive operation Mode 1 transmit operation MSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0 113Start Serr RXD 114 Mode 2 baud rate Mode OutlineMode 2 transmit operation Mode 2 receive operation Mode 2 Uart error detection Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port Internal BUS Write Start TBB Sbuf TXD To Sbuf 118 Mode 3 baud rate Mode 3 receive operation Mode 3 transmit operation Mode 3 Uart error detection 122 123 Inhibit F E D C B a Input QHSHIFT/ Load Serial ClockRXD PX.X TXD RX.X TXD CLK Qhqg QF QE Qdqc QB QARXD TXD PX.X PX.X RXD TXD SHIFT/ Load Serial Clock 126Output PX.X Control RXD Input PX.X Control TXD 127 42 lnput/output extension example timing chart MSM80C154S/83C154S/85C154HVS Multi-processor systems TXD RXDMaster Slave 18 lnterrupt addresses Interrupt 130 Interrupt controlEquivalent circuit ET1 19 lnterrupt enable register IE, 0A8H 20 nterrupt priority register IP, 0B8H PX1 Priority interrupt routine flow Clrea 21 Non-priority interrupt order of preference 22 TCON88H register External interrupt signal 0 and 1 level detectionTF1 TR1 TF0 IE1 IT1 IE0 IT0 BUS Tcon Reset External interrupt signal 0 and 1 trigger detectionPage 139 Page 141 Page 143 Page 145 Idle mode Idle setting CPU Power Down Xtal TIMER, S-I/O Interrupt 147Xtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL 148 23 CPU pin details in idle mode 149 Idle 150 55Idlemodesettingtime Soft power down mode PD setting 152 Mode equivalent circuitCPU Clock Pcon 87H Control Smod HPD RPD GF1 Reset END PdresetPCON5RPD Pdreset 153 154 TIMER0 155 24 CPU pin details ALF=0 in soft power down mode PD Soft power down mode setting Time chart internal ROM mode156 Soft 158 25 CPU pin details ALF=1 in soft power down mode PD 159 Down 160 63Softpowerdownmodesetting Hard power down mode HPD setting Hard power down 162Xtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL 163 26 CPU pin details ALF=0 in hard power down mode HPD Mode 164 165 166 27 CPU pin details ALF=1 in hard power down mode HPD 167 168 68Hardpowerdownmodesetting Cancellation by CPU resetting Reset pin By reset internal ROM mode 170MSM80C154S/83C154S/85C154HVS 171 172 173 By reset external ROM mode 174 Mode by reset internal ROM mode 175 Mode by reset external ROM mode Smod HPD RPD GF1 GF0 IDL 29 Power control register Pcon 87H 177 IDLE, PD Mode Interrupt Restart INT 179 180 Internal ROM mode 181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense Restart from idle mode by Or 1 external ROM mode184 185 Or 1 internal ROM mode 186 External ROM mode Internal Specifications 188 Back up with hard power down mode Back 189 190 INPUT/OUTPUT PortsPage Outline PortPort 0 internal equivalent circuit 193 Internal BUS ReadWPO Modify Port 0 pin table 194 Port 196 Control Modify Port Read WP1Port 1 internal equivalent circuit 197 OFFInternal BUS Read OFF 198 On P3 On P2 Internal BUS Readoff N 199 200 Port 1 CPU control pin tablePort 1 pin table PC/DATA DPH Port Read Modify WP2 ControlPort 2 internal equivalent circuit PORT2 202 WP3 Internal BUS Control Modify Read Data 204 Port 3 CPU control pin function tablePort 3 pin table INPUT/OUTPUT Ports Power Down Iocon 0F8H 206Modify Port Read Internal BUS INPUT/OUTPUT Ports 12 NPN transistor direct connection circuit CPU 1 OUT CPU 0 OUT 209 One machine cycle instruction output timing Port Output Timing Two machine cycle instruction output timing 16 Two machine cycle instruction port output time chart Port Data Manipulating Instructions 213 214 MSM80C154/83C154/85C154 Electrical Characteristics Operational Ranges Absolute Maximum Ratings VCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85C DC CharacteristicsPort 0, ALE, Psen SSV IV CC 218 219 DC Characteristics Repeated for specified output pins Repeated for specified input pinsMeasuring circuits Input logic for specified status External Program Memory Access AC Characteristics External program memory read cycle 222ALE Psen Port Instr Output External Data Memory Access AC Characteristics 224 External data memory read cycleExternal data memory write cycle Output Data Setup to Clock Rising Edge TQVXH Machine Cycle ALE Shift Clock Output Data Input Data 226 Input/output signal AC Characteristics Measuring ConditionsFloating Test Point XTAL1 External Clock Input Waveform Conditions Exterminal Oscillator Signal Description of Instructions Page Description of Instructions Description of Instruction Symbols List of Instructions MSM80C154S/MSM83C154SInstruction table Address in this description Simplified Description of Instructions CLR a CPL a RL a RLC a RR a RRC a Swap a 235 236 MOV XRL MOV Dptr 238CLR Setb Movc A, @A+PC 239 240 Ljmp Interrupt Enable AjmpSjmp JMP @A+DPTR Then Else Cjne 242 Then Else Djnz 243 244 External RAM 245Movx A, @DPTR NOP Acall code address Absolute call within 2K bytes Detailed Description of MSM80C154S/MSM83C154S Instructions ADD A, #data Add immediate data 247RS1 248 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address 249 ADD A, Rr Add register 250 MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory 251 Addc A, #data Add carry plus immediate data to accumulator 252 253 ADD A, Rr Add carry plus register to accumulator 254 255 Ajmp code address Absolute jump within 2K byte 256 257 ANL A, @Rr Logical and indirect address to accumulator 258 259 ANL A, data address Logical and memory to accumulator 260 261 ANL C,/bit address Logical and complement bit to carry flag 262 263 ANL data address, a Logical and accumulator to memory 264 LOC OBJ Source 265Testajmp TEST1 Compcjne @R1, #05H, Test 266 Cjne A, #0AH, SS1 LOC OBJ Source 267SS1MOV R7, a Compcjne A, #0AH, SS1 268 Cjne A, 50H, Next LOC OBJ Source 269Compcjne A, 50H, Next Callcall Test Compared data is not equal. If the compared data is equal 270 Countinc R4 271 272 MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator 273 CLR C Clear carry flag 274 MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit 275 CPL a Complement accumulator 276 MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag 277 CPL bit address Complement bit 278 MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator 279 280 281 DEC a Decrement accumulator 282 MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register 283 DEC data address Decrement memory MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by B 284AC F0 RS1 RS0 OV F1 285 Djnz R1, Loop LOC OBJ Source 286Loopadd A, R7 Countdjnz R1, Loop 287 288 Djnz 57H, Loop LOC OBJ SourceCountdjnz 57H, Loop 289 INC @Rr Increment indirect address 290 MSM80C154S/83C154S/85C154HVS INC a Increment accumulator 291 INC Dptr Increment data pointerRS1 RS0 PSW DPH DPL 292 MSM80C154S/83C154S/85C154HVS INC Rr Increment register 293 INC data address Increment memory 294 295 Bittsjb 34.3, EnterACA0 Entermov R4, 0A0H 296 297 298 Checkacall Addr 299Jmpcjc Carry Carryinc @R1 Byte Description 300 301 JNB bit address, code address Jump if bit is not set 302 Testjnb 37.3, ExitExitmov A, @R0 303 JNC code address Jump if carry is not set 304 Testjnc ExitExitmov B, ACC 305 JNZ code address Jump if accumulator is not JNZ Test LOC OBJ Source 306Checkjnz Test Testmov R3, a 307 JZ code address Jump if accumulator is not JZ Empty LOC OBJ Source 308Emptyinc a Checkjz Empty 309 Lcall code address Long call 310 MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump MOV @Rr, #data Move immediate data to indirect address 3116AH 6CH 312 313 MOV @Rr, data address Move memory to indirect address 314 315 MOV A, @Rr Move indirect address to accumulator 316 317 MOV A, data address Move memory to accumulator 318 MOV DPTR, #data Move immediate data to data pointer 319DPH·DPL 320 321 MOV Rr, a Move accumulator to register 5AH 322 323 MOV bit address, C Move carry flag to bit 324 325 MOV data address, @Rr Move indirect address to memory 326 MOV data address, Rr Move register to memory 3276BH 328 Movc A, @A+DPTR 329 330 62CCH 331 332 333 DPL DPH57AFH 334 335 MUL AB Multiply accumulator by B 336 MSM80C154S/83C154S/85C154HVS NOP No operation 337 ORL A, #data Logical or immediate data to accumulator 338 339 ORL A, Rr Logical or register to accumulator 340 341 ORL C, bit address Logical or bit to carry flag 342 343 ORL data address, #data Logical or immediate data to memory 344 345 POP data address Pop stack to memory 346 347 RET Return from subroutine, non interrupt 348 RL a Rotate accumulator left 349RS1 RS0 OV F1 P PSW 350 351 RR a Rotate accumulator right 352 353 Setb C Set carry flag 354 MSM80C154S/83C154S/85C154HVS Setb bit address Set bit 355 Sjmp code address Short jump 356 Sjumpsjmp CheckCheckrlc a 357 358 359 Subb A, Rr Substract register from accumulator with borrow 360 361 Swap a Exchange nibble in accumulator 362 363 XCH A, Rr Exchange register with accumulator 7AH 364 365 366 367 368 369 370 371