Sonic Alert msm80154s, msm83c154s Introduction, MSM80C154S/MSM83C154S/MSM85C154HVS Outline

INTRODUCTION

1. INTRODUCTION

1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline

MSM80C154S/MSM83C154S/MSM85C154HVS are single-chip 8-bit fully static microcon- trollers featuring high performance and low power consumption. All MSM80C31F /MSM80C51F instructions and functions have been retained.

Apart from being without the internal program memory (ROM), MSM80C154S is identical to MSM83C154S. And the difference between MSM85C154HVS and MSM83C154S is that the internal program memory (ROM) in MSM83C154S is replaced by an external ROM connected to MSM85C154HVS by using a piggy-back package.

While the MSM83C154S microcontroller integrates a 16384-word ⋅ 8-bit program memory (ROM) in a single chip, MSM80C154S/MSM83C154S/MSM85C154HVS all feature comput- er functions including a 256-word ⋅ 8-bit data memory (RAM), 32 input/ output ports, three 16-bit timer/counters, six interrupts, serial I/O, an 8-bit parallel processing circuit, and a clock generator.

The internal operation in these CPUs is based on an instruction code address method for greater efficiency. In this method, operations are specified in the instruction code (OP) section, and the objective registers are specified by part of that instruction code and the second or third byte following the code. A feature of this method is the ability to achieve several operations by simply changing the manipulation register designation in a single instruction code.

Inclusion of 8-bit multiplication and division instructions further increases the processing capacity of these CPUs.

In addition to expansion of the bit processing area, a comprehensive range of bit processing instructions has also been included. Processing operations include logical processing of the carry flag and specified bit within each register, transfer between the carry flag and specified bit in certain registers, transfer of specified bits between different registers, setting, resetting, and complement of the specified bit in each register, and execution of various bit tests within a wide area.

To make a relative jump after the execution of a bit test instruction, jumps can be made within a wide address range between –128 and +127 relative to the address of the instruction and there is no page field restriction.

The contents of specified registers can be saved in stack by using the PUSH instruction, and the saved contents can be returned from stack to a specified register by the POP instruction. Absolute interrupt priority can be allocated to any interrupt when in priority circuit operation mode. And by controlling only the interrupt enable register (IE) when in priority circuit stop mode, multi-level interrupt processing can be executed to make interrupt processing much easier than in conventional CPUs.

Employing the low-power consumption feature of C-MOS devices, these CPUs are designed to operate in a number of “CPU power down” modes. In idle mode the IDL bit in the power control register (PCON) is set to “1” to halt CPU operations while the oscillator continues to run. In soft power down mode the PD bit in the power control register is set to “1” to halt CPU operations as well as the oscillator. And in hard power down mode where the HPD bit in the power control register is set in advance to “1”, CPU operations and the oscillator are stopped if the HPDI pin (P3.5) power failure detect signal level is changed from “1” to “0”. CPU power down modes can be cancelled by resetting the CPU via reset pin and restarting execution from address 0, by restarting execution from the relevant interrupt address, or by resuming

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