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Sonic Alert msm80154s, msm83c154s, msm85c154hvs user manual 264, Then

Models: msm83c154s msm85c154hvs msm80154s

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MSM80C154S/83C154S/85C154HVS

19.CJNE @Rr, #data, code address

(Compare indirect address to immediate data, jump if not equal)

Instruction code

Byte 1

#data

Byte 2

Relative offset

Byte 3

Operations

: (PC)←(PC)+3

IF ((Rr))≠#data

r=0 or 1

THEN

(PC)←(PC)+relative offset

IF ((Rr))<#data

r=0 or 1

THEN

(C)←1

ELSE

(C)←0

Number of bytes

: 3

Number of cycles

: 2

Flags

RS1

RS0

(PSW)

•

Description

: The data memory location contents addressed by the register r

contents are compared with an immediate data value. Control is

shifted to a relative jump address if the compared data is not

equal. If the compared data is equal, control is shifted to the next address following this instruction. The carry flag is set to 1 if the immediate data value is greater than the specified address contents, but is set to 0 if otherwise.

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Sonic Alert msm80154s, msm83c154s, msm85c154hvs user manual 264, Then

Contents

MSM80C154S MSM83C154S Page Contents 2.5.4 Reset Schmitt trigger circuit CPU internal status by reset2.5.2 2.5.3Special function registers for serial port 101 2.1 Power down mode3.4.2 T2EXtimer/counter 2 external flag input detector 3.1142 Multi-processor systems 128129 140210 KW Pull-Up Resistance Setting for Quasi-bidirectional Input207 208Introduction Page MSM80C154S/MSM83C154S/MSM85C154HVS Outline IntroductionMSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154SRS/MSM83C154SRS MSM80C154S/MSM83C154S pin layoutsMSM80C154S/MSM83C154S pin layout top view Applicable Packages MSM80C154S/MSM83C154S external dimensions 1 MSM80C154S/MSM83C154S external dimensionsMSM80C154STS/MSM83C154STS MSM85C154HVS pin layout and external dimensions 2 MSM85C154HVS pin layout and external dimensionsRegister Address SignalTIMER/COUNTER 0&1 Interrupt Serial IO Special FunctionTH1 TL1 TH0 TL0 Tmod Tcon ROM SpecialDPL PLA Register Address Sense AMPTH1 TL1 TH0 TL0 Signal DPHT2CON TL2 TH2 AMP ACC TR2 TR1 Address DecoderOutline of MSM80C154S/MSM83C154S timing Timing and Control9MSM80C154S/MSM83C154S TimingMajor synchronizing signals Movx A, @Rr External program memory read cycle timing chartXTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT 13 MSM80C154S Movx A, @DPTR execution 12 MSM80C154S Movx @Rr, a executionXTAL1 ALE Psen MOV direct, Port 0, 1, 2, 3 executionPIN Data CPU Data PIN Data Stable Sampled 16 MSM83C154S Movx A, @Rr execution 4 MSM83C154S fundamental operation time charts19 MSM83C154S Movx @DPTR, a execution 18 MSM83C154S Movx A, @DPTR execution20 MSM83C154S MOV direct, PORT0, 1, 2, 3 execution PIN Data PIN Data Stable CPU Data SampledPLA WIR Instruction Register IR and Instruction Decoder PLAAIR PLA WairPSW0D0H CY AC F0 RS1 RS0 OV F1 P Arithmetic Operation SectionCPU Internal Data BUS Program Counter24 MSM80C154S/MSM83C154S program area Program Memory and External Data MemoryALE Latch System Configuration Dptr XTAL1 ALE Psen Page By register R0 or R1 MSM80C154S/MSM83C154SData Control Page Oscillators XTAL1 XTAL2 Crystal resonator connection diagramClock XTAL2 Supply of 50% duty clockCPU Reset Control CPU ResettingOutline 5Resetexecution ROM modeChart Chart XTAL1 Psen ALE Reset Schmitt trigger gate detector time chart MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuitDenotes direct resetting even if XTAL1·2 has stopped CPU internal status by resetMSM80C154S/MSM83C154S reset internal status EA CPU Memory Separate Internal Specifications Page Internal Data Memory RAM and Special Function Registers Internal SpecificationsData memory and special function register layout Internal data memory RAM Internal Data Memory RAMRAM layout diagram User Data RAM Internal data memory registers R0 thru R7Program status word PSW RS0PC1 MSM80C154S/83C154S/85C154HVS StackStack storage layout PC5Internal data memory indirect addressing Lnternal Data Memory RAM Operating ProceduresDEC Rr bit arrangement Register designation table CLR bit address bit arrangement Internal data memory 1-bit data designation2EH Bit designation tableAddressing combination table 2AH 2BHSpecial Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon SCON.0 SCON.6 SM1 SM0 ModeMSB LSB Scon SM0 SM1 SM2 REN TB8 RB8ET2 Interrupt enable register IEMSB LSB ET2 ET1 EX1 ET0 EX0PCT PT2 PT1 PX1 PT0 PX0 MSM80C154S/83C154S/85C154HVS Interrupt priority register IPPCT Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon TF2 Timer 2 control register T2CONTF2 EXF2 EXEN2Timer control register Tcon 88H Timer/Counters 0, 1 and 2 4.5.1 OutlineTimer/counters 0 and 1 4.5.2.1 Outline Timer/counter 0 and 1 counting controlOverall clock input control Circuit for timer/counters 0Timer mode register Tmod 89H Timer External clock detector circuit for timer/counters 0PD & HPD Detector circuit operational time chart Counting control of timer/counters 0 and 1 by INT pinTimer Gate TR0 INT0 RUN Stop TR1 INT1 Timer ClockDetector Timer Counter 11 Timer mode register Tmod 89HMode Latch Detector TF1 TL1 TH1 5BITS 8BITS O Clock T0 PIN Detector Port TR0 Gate INT0 PIN DataDetector TF0 TL0 TH0 5BITS 8BITS T1 PIN Detector Port TR1 Gate INT1 PIN DataMSM80C154S/83C154S/85C154HVS Mode TH1 8BITS O Clock Detector TF0TH0 8BITS Latch Detector TF1MSM80C154S/83C154S/85C154HVS Mode Reload Data Xtal T0 PIN Detector Port TF08BITS TR0 Gate INT0 PIN 8BITS DataTH0 C 8BITS Detector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN DataLatch Xtal TL0 8BITS Detector TF1Serr IZC 2.5.6 32-bit timer modeT0 PIN Detector Iocon 0F8H19 T0, T1 external clock detector circuit Timer ResetInternal Specifications 12 Timer 2 control register T2CON 0C8H Mode 1 or 3 has been setBit is 0, and valid when To 0 by software Must be reset to 0 by softwareTimer/counter 2 operation modes 3.3.1 16-bit auto reload modeTL2 TH2 BIT 3.3.2 16-bit capture modeTR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 Interrupt RCLK=0 TCLK=021 Timer/counter 2 16-bit capture mode circuit 3.3.3 16-bit baud rate generator modeBaud Reset Timer Counter Clock 3.4.2 T2EX timer/counter 2 external flag input detectorReset Timer Counter T2EX Detector PD & HPD O Clock Timer/counter detector circuitSerial Port RX Control Input Shift Register 100Sbuf R Internal Specifications 15 Scon 10216 Serial port operation modes Sbuf serial port buffer registerTclk RclkMSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 transmit operation Mode 0 baud rateMode 0 receive operation 107 Port modeTiming chart Serial port mode108 109 Mode 1 baud rate MSM80C154S/83C154S/85C154HVS Mode OutlineMode 1 receive operation Mode 1 transmit operationMSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection 113 Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0Start Serr RXD 114 Mode 2 receive operation Mode OutlineMode 2 baud rate Mode 2 transmit operationMode 2 Uart error detection Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port Internal BUS Write Start TBB Sbuf TXD To Sbuf118 Mode 3 baud rate Mode 3 receive operation Mode 3 transmit operationMode 3 Uart error detection 122 123 RX.X TXD QHSHIFT/ Load Serial ClockInhibit F E D C B a Input RXD PX.X TXDPX.X RXD TXD Qhqg QF QE Qdqc QB QACLK RXD TXD PX.XRXD Input PX.X Control TXD 126SHIFT/ Load Serial Clock Output PX.X Control127 42 lnput/output extension example timing chartTXD RXD MSM80C154S/83C154S/85C154HVS Multi-processor systemsMaster Slave 18 lnterrupt addresses InterruptInterrupt control 130Equivalent circuit ET1 19 lnterrupt enable register IE, 0A8H20 nterrupt priority register IP, 0B8H PX1Priority interrupt routine flow Clrea 21 Non-priority interrupt order of preference IE1 IT1 IE0 IT0 External interrupt signal 0 and 1 level detection22 TCON88H register TF1 TR1 TF0BUS Tcon Reset External interrupt signal 0 and 1 trigger detectionPage 139 Page 141 Page 143 Page 145 Idle mode Idle setting CPU Power Down147 Xtal TIMER, S-I/O InterruptXtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL 148 23 CPU pin details in idle mode149 Idle150 55IdlemodesettingtimeSoft power down mode PD setting Pcon 87H Control Smod HPD RPD GF1 Mode equivalent circuit152 CPU Clock153 PdresetReset END PCON5RPD Pdreset154 TIMER0155 24 CPU pin details ALF=0 in soft power down mode PDTime chart internal ROM mode Soft power down mode setting156 Soft 158 25 CPU pin details ALF=1 in soft power down mode PD159 Down160 63SoftpowerdownmodesettingHard power down mode HPD setting 162 Hard power downXtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL 163 26 CPU pin details ALF=0 in hard power down mode HPDMode 164165 166 27 CPU pin details ALF=1 in hard power down mode HPD167 168 68HardpowerdownmodesettingCancellation by CPU resetting Reset pin 170 By reset internal ROM modeMSM80C154S/83C154S/85C154HVS 171 172 173 By reset external ROM mode174 Mode by reset internal ROM mode175 Mode by reset external ROM modeSmod HPD RPD GF1 GF0 IDL 29 Power control register Pcon 87H177 IDLE, PD Mode Interrupt RestartINT 179 180 Internal ROM mode181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense Or 1 external ROM mode Restart from idle mode by184 185 Or 1 internal ROM mode186 External ROM modeInternal Specifications 188 Back up with hard power down modeBack 189190 INPUT/OUTPUT PortsPage Port OutlinePort 0 internal equivalent circuit Internal BUS Read 193WPO Modify Port 0 pin table 194Port Control Modify Port Read WP1 196Port 1 internal equivalent circuit OFF 197Internal BUS Read OFF 198 On P3 On P2 Internal BUS Readoff N 199Port 1 CPU control pin table 200Port 1 pin table DPH Port Read Modify WP2 Control PC/DATAPort 2 internal equivalent circuit PORT2 202WP3 Internal BUS Control Modify Read DataPort 3 CPU control pin function table 204Port 3 pin table INPUT/OUTPUT Ports 206 Power Down Iocon 0F8HModify Port Read Internal BUS INPUT/OUTPUT Ports 12 NPN transistor direct connection circuit CPU 1 OUTCPU 0 OUT 209One machine cycle instruction output timing Port Output TimingTwo machine cycle instruction output timing 16 Two machine cycle instruction port output time chartPort Data Manipulating Instructions 213 214 MSM80C154/83C154/85C154Electrical Characteristics Operational Ranges Absolute Maximum RatingsSSV IV CC DC CharacteristicsVCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85C Port 0, ALE, Psen218 219 DC CharacteristicsInput logic for specified status Repeated for specified input pinsRepeated for specified output pins Measuring circuitsExternal Program Memory Access AC Characteristics Instr 222External program memory read cycle ALE Psen PortOutput External Data Memory Access AC CharacteristicsExternal data memory read cycle 224External data memory write cycle Output Data Setup to Clock Rising Edge TQVXH Machine Cycle ALE Shift Clock Output Data Input Data 226Test Point AC Characteristics Measuring ConditionsInput/output signal FloatingXTAL1 External Clock Input Waveform Conditions Exterminal Oscillator SignalDescription of Instructions Page Description of Instructions Description of Instruction Symbols MSM80C154S/MSM83C154S List of InstructionsInstruction table Address in this description Simplified Description of InstructionsCLR a CPL a RL a RLC a RR a RRC a Swap a 235236 MOV XRLSetb 238MOV Dptr CLRMovc A, @A+PC 239240 JMP @A+DPTR Interrupt Enable AjmpLjmp SjmpThen Else Cjne 242Then Else Djnz 243244 NOP 245External RAM Movx A, @DPTRAcall code address Absolute call within 2K bytes Detailed Description of MSM80C154S/MSM83C154S Instructions247 ADD A, #data Add immediate dataRS1 248 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address249 ADD A, Rr Add register250 MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory251 Addc A, #data Add carry plus immediate data to accumulator252 253 ADD A, Rr Add carry plus register to accumulator254 255 Ajmp code address Absolute jump within 2K byte256 257 ANL A, @Rr Logical and indirect address to accumulator258 259 ANL A, data address Logical and memory to accumulator260 261 ANL C,/bit address Logical and complement bit to carry flag262 263 ANL data address, a Logical and accumulator to memory264 Compcjne @R1, #05H, Test 265LOC OBJ Source Testajmp TEST1266 Compcjne A, #0AH, SS1 267Cjne A, #0AH, SS1 LOC OBJ Source SS1MOV R7, a268 Callcall Test 269Cjne A, 50H, Next LOC OBJ Source Compcjne A, 50H, NextCompared data is not equal. If the compared data is equal 270Countinc R4 271272 MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator273 CLR C Clear carry flag274 MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit275 CPL a Complement accumulator276 MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag277 CPL bit address Complement bit278 MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator279 280 281 DEC a Decrement accumulator282 MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register283 DEC data address Decrement memory284 MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by BAC F0 RS1 RS0 OV F1 285 Countdjnz R1, Loop 286Djnz R1, Loop LOC OBJ Source Loopadd A, R7287 Djnz 57H, Loop LOC OBJ Source 288Countdjnz 57H, Loop 289 INC @Rr Increment indirect address290 MSM80C154S/83C154S/85C154HVS INC a Increment accumulatorDPH DPL INC Dptr Increment data pointer291 RS1 RS0 PSW292 MSM80C154S/83C154S/85C154HVS INC Rr Increment register293 INC data address Increment memory294 Bittsjb 34.3, Enter 295ACA0 Entermov R4, 0A0H 296 297 298 Carryinc @R1 299Checkacall Addr Jmpcjc CarryByte Description 300301 JNB bit address, code address Jump if bit is not setTestjnb 37.3, Exit 302Exitmov A, @R0 303 JNC code address Jump if carry is not setTestjnc Exit 304Exitmov B, ACC 305 JNZ code address Jump if accumulator is notTestmov R3, a 306JNZ Test LOC OBJ Source Checkjnz Test307 JZ code address Jump if accumulator is notCheckjz Empty 308JZ Empty LOC OBJ Source Emptyinc a309 Lcall code address Long call310 MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump311 MOV @Rr, #data Move immediate data to indirect address6AH 6CH 312313 MOV @Rr, data address Move memory to indirect address314 315 MOV A, @Rr Move indirect address to accumulator316 317 MOV A, data address Move memory to accumulator318 319 MOV DPTR, #data Move immediate data to data pointerDPH·DPL 320 321 MOV Rr, a Move accumulator to register5AH 322323 MOV bit address, C Move carry flag to bit324 325 MOV data address, @Rr Move indirect address to memory326 327 MOV data address, Rr Move register to memory6BH 328 Movc A, @A+DPTR 329330 62CCH 331332 DPL DPH 33357AFH 334 335 MUL AB Multiply accumulator by B336 MSM80C154S/83C154S/85C154HVS NOP No operation337 ORL A, #data Logical or immediate data to accumulator338 339 ORL A, Rr Logical or register to accumulator340 341 ORL C, bit address Logical or bit to carry flag342 343 ORL data address, #data Logical or immediate data to memory344 345 POP data address Pop stack to memory346 347 RET Return from subroutine, non interrupt348 349 RL a Rotate accumulator leftRS1 RS0 OV F1 P PSW 350 351 RR a Rotate accumulator right352 353 Setb C Set carry flag354 MSM80C154S/83C154S/85C154HVS Setb bit address Set bit355 Sjmp code address Short jumpSjumpsjmp Check 356Checkrlc a 357 358 359 Subb A, Rr Substract register from accumulator with borrow360 361 Swap a Exchange nibble in accumulator362 363 XCH A, Rr Exchange register with accumulator7AH 364365 366 367 368 369 370 371