234

Classifi- cation

Arithmetic operation instructions

Mnemonic

 

 

Instruction code

 

 

Byte

Cycle

Description

 

Page

 

 

 

 

 

 

 

 

 

D7 D6 D5 D4 D3 D2 D1 D0

 

 

 

 

 

 

 

 

ADD

A, Rr

0

0

1

0

1

r2

r1

r0

1

1

(AC),(OV),(C),(A)(A)+(Rr)

r=0~7

249

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

A, direct

0

0

1

0

0

1

0

1

2

1

(AC),(OV),(C),(A)(A)+(direct address)

250

a7 a6 a5 a4 a3 a2 a1 a0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

A, @Rr

0

0

1

0

0

1

1

r

1

1

(AC),(OV),(C),(A)(A)+((Rr))

r=0 or 1

248

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

A, #data

0

0

1

0

0

1

0

0

2

1

(AC),(OV),(C),(A)(A)+#data

 

247

I7 I6 I5 I4 I3 I2 I1 I0

 

 

 

 

 

 

 

 

ADDC

A, Rr

0

0

1

1

1

r2

r1

r0

1

1

(AC),(OV),(C),(A)(A)+(C)+(Rr)

r=0~7

253

ADDC

A, direct

0

0

1

1

0

1

0

1

2

1

(AC),(OV),(C),(A)(A)+(C)+(direct address)

254

a7 a6 a5 a4 a3 a2 a1 a0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDC

A, @Rr

0

0

1

1

0

1

1

r

1

1

(AC),(OV),(C),(A)(A)+(C)+((Rr))

r=0 or 1

252

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDC

A, #data

0

0

1

1

0

1

0

0

2

1

(AC),(OV),(C),(A)(A)+(C)+#data

 

251

I7 I6 I5 I4 I3 I2 I1 I0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUBB

A, Rr

1

0

0

1

1

r2

r1

r0

1

1

(AC),(OV),(C),(A)(A)–((C)+(Rr))

r=0~7

359

SUBB

A, direct

1

0

0

1

0

1

0

1

2

1

(AC),(OV),(C),(A)(A)–((C)+(direct address))

360

a7 a6 a5 a4 a3 a2 a1 a0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUBB

A, @Rr

1

0

0

1

0

1

1

r

1

1

(AC),(OV),(C),(A)(A)–((C)+((Rr)))

r=0 or 1

358

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUBB

A, #data

1

0

0

1

0

1

0

0

2

1

(AC),(OV),(C),(A)(A)–((C)+#data)

 

357

I7 I6 I5 I4 I3 I2 I1 I0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUL

AB

1

0

1

0

0

1

0

0

1

4

(AB)(A)(B)

 

335

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIV

AB

1

0

0

0

0

1

0

0

1

4

(A) quotient, (B) remainder (A)/(B)

 

284

DA

A

1

1

0

1

0

1

0

0

1

1

When the contents of accumulator bit 0 thru 3 exceed

278

 

 

 

 

 

 

 

 

 

 

 

 

9, and when the auxiliary carry (AC) is 1, 6 is added to

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 0 thru 3. And if examination od bits 4 thru 7 shows

 

 

 

 

 

 

 

 

 

 

 

 

 

that the result of adding the carry following correction of

 

 

 

 

 

 

 

 

 

 

 

 

 

the lower order bits 0 thru 3 by 6 is in excess of 9, or

 

 

 

 

 

 

 

 

 

 

 

 

 

carry (C) is 1, 6 is added to bits 4 thru 7. If a carry is

 

 

 

 

 

 

 

 

 

 

 

 

 

generated as a result, 1 is set in the carry flag.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note that “data address” is represented as “direct

7.4 Simplified Description of Instructions

MSM80C154S/83C154S/85C154HVS

address” in this description.

 

 

Page 241
Image 241
Sonic Alert msm80154s, msm83c154s, msm85c154hvs Simplified Description of Instructions, Address in this description