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Sonic Alert msm85c154hvs, msm83c154s, msm80154s user manual 346

Models: msm83c154s msm85c154hvs msm80154s

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MSM80C154S/83C154S/85C154HVS

87. PUSH data address (Push memory onto stack)

			7										0
Instruction code	:		1		1	0			0	0	0	0	0	Byte 1
			7										0
Data address		a7		a6		a5		a4		a3	a2	a1	a0	Byte 2
Operations	: (SP)←(SP)+1
		((SP))←(data address)
Number of bytes	: 2
Number of cycles	: 2
Flags	:		C	AC		F0		RS1		RS0	OV	F1	P
(PSW)
(PSW)
Description
Description	: The stack pointer is incremented by 1, and the specified data
		address contents are pushed in the stack addressed by the
		stack pointer.
Example PUSH P1
	7								0
Instruction code	:	1	1	0	0	0	0	0	0	Byte 1
	7								0
		1	0	0	1	0	0	0	0	Byte 2

Before execution Port 1(90H)

1 1 0 1 0 1 0 1

70 Stack pointer

0 0 0 1 0 0 0 0

11H (Stack)

0 0 0 0 0 0 0 0

After execution Port 1(90H)

1 1 0 1 0 1 0 1

70 Stack pointer

0 0 0 1 0 0 0 1

11H (Stack)

1 1 0 1 0 1 0 1

346

Page 353

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Sonic Alert msm85c154hvs, msm83c154s, msm80154s user manual 346

Contents

MSM80C154S MSM83C154S Page Contents 2.5.2 Reset Schmitt trigger circuit CPU internal status by reset2.5.3 2.5.43.4.2 T2EXtimer/counter 2 external flag input detector Power down mode3.1 Special function registers for serial port 101 2.1129 Multi-processor systems 128140 142207 KW Pull-Up Resistance Setting for Quasi-bidirectional Input208 210Introduction Page MSM80C154S/MSM83C154S/MSM85C154HVS Outline IntroductionMSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154SRS/MSM83C154SRS MSM80C154S/MSM83C154S pin layoutsMSM80C154S/MSM83C154S pin layout top view Applicable Packages MSM80C154S/MSM83C154S external dimensions 1 MSM80C154S/MSM83C154S external dimensionsMSM80C154STS/MSM83C154STS MSM85C154HVS pin layout and external dimensions 2 MSM85C154HVS pin layout and external dimensionsTIMER/COUNTER 0&1 Interrupt Serial IO SignalSpecial Function Register AddressDPL PLA Register Address ROM SpecialSense AMP TH1 TL1 TH0 TL0 Tmod TconT2CON TL2 TH2 AMP ACC TR2 TR1 Signal DPHAddress Decoder TH1 TL1 TH0 TL0Outline of MSM80C154S/MSM83C154S timing Timing and Control9MSM80C154S/MSM83C154S TimingMajor synchronizing signals XTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT External program memory read cycle timing chartMovx A, @Rr 13 MSM80C154S Movx A, @DPTR execution 12 MSM80C154S Movx @Rr, a executionPIN Data CPU Data PIN Data Stable Sampled MOV direct, Port 0, 1, 2, 3 executionXTAL1 ALE Psen 16 MSM83C154S Movx A, @Rr execution 4 MSM83C154S fundamental operation time charts19 MSM83C154S Movx @DPTR, a execution 18 MSM83C154S Movx A, @DPTR execution20 MSM83C154S MOV direct, PORT0, 1, 2, 3 execution PIN Data PIN Data Stable CPU Data SampledAIR Instruction Register IR and Instruction Decoder PLAPLA Wair PLA WIRPSW0D0H CY AC F0 RS1 RS0 OV F1 P Arithmetic Operation SectionCPU Internal Data BUS Program Counter24 MSM80C154S/MSM83C154S program area Program Memory and External Data MemoryALE Latch System Configuration Dptr XTAL1 ALE Psen Page By register R0 or R1 MSM80C154S/MSM83C154SData Control Page Oscillators XTAL1 XTAL2 Crystal resonator connection diagramClock XTAL2 Supply of 50% duty clockOutline CPU ResettingCPU Reset Control 5Resetexecution ROM modeChart Chart XTAL1 Psen ALE Reset Schmitt trigger gate detector time chart MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuitMSM80C154S/MSM83C154S reset internal status CPU internal status by resetDenotes direct resetting even if XTAL1·2 has stopped EA CPU Memory Separate Internal Specifications Page Internal Data Memory RAM and Special Function Registers Internal SpecificationsData memory and special function register layout Internal data memory RAM Internal Data Memory RAMRAM layout diagram Program status word PSW Internal data memory registers R0 thru R7RS0 User Data RAMStack storage layout MSM80C154S/83C154S/85C154HVS StackPC5 PC1Internal data memory indirect addressing Lnternal Data Memory RAM Operating ProceduresDEC Rr bit arrangement Register designation table CLR bit address bit arrangement Internal data memory 1-bit data designationAddressing combination table Bit designation table2AH 2BH 2EHSpecial Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon MSB LSB Scon SCON.6 SM1 SM0 ModeSM0 SM1 SM2 REN TB8 RB8 SCON.0MSB LSB Interrupt enable register IEET2 ET1 EX1 ET0 EX0 ET2PCT MSM80C154S/83C154S/85C154HVS Interrupt priority register IPPCT PT2 PT1 PX1 PT0 PX0 Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon TF2 EXF2 Timer 2 control register T2CONEXEN2 TF2Timer/counters 0 and 1 4.5.2.1 Outline Timer/Counters 0, 1 and 2 4.5.1 OutlineTimer/counter 0 and 1 counting control Timer control register Tcon 88HOverall clock input control Circuit for timer/counters 0Timer mode register Tmod 89H PD & HPD External clock detector circuit for timer/counters 0Timer Detector circuit operational time chart Counting control of timer/counters 0 and 1 by INT pinDetector Timer ClockTimer Gate TR0 INT0 RUN Stop TR1 INT1 Mode 11 Timer mode register Tmod 89HTimer Counter Detector TF0 TL0 TH0 5BITS 8BITS T0 PIN Detector Port TR0 Gate INT0 PIN DataT1 PIN Detector Port TR1 Gate INT1 PIN Data Latch Detector TF1 TL1 TH1 5BITS 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode TH0 8BITS Detector TF0Latch Detector TF1 TH1 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode 8BITS TR0 Gate T0 PIN Detector Port TF0INT0 PIN 8BITS Data Reload Data XtalLatch Xtal Detector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN DataTL0 8BITS Detector TF1 TH0 C 8BITST0 PIN Detector 2.5.6 32-bit timer modeIocon 0F8H Serr IZC19 T0, T1 external clock detector circuit Timer ResetInternal Specifications Bit is 0, and valid when Mode 1 or 3 has been set12 Timer 2 control register T2CON 0C8H Timer/counter 2 operation modes Must be reset to 0 by software3.3.1 16-bit auto reload mode To 0 by softwareTR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 Interrupt 3.3.2 16-bit capture modeRCLK=0 TCLK=0 TL2 TH2 BIT21 Timer/counter 2 16-bit capture mode circuit 3.3.3 16-bit baud rate generator modeBaud Reset Timer Counter T2EX 3.4.2 T2EX timer/counter 2 external flag input detectorReset Timer Counter Clock Detector PD & HPD O Clock Timer/counter detector circuitSerial Port Sbuf R 100RX Control Input Shift Register Internal Specifications 15 Scon 102Tclk Sbuf serial port buffer registerRclk 16 Serial port operation modesMSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 receive operation Mode 0 baud rateMode 0 transmit operation 107 Port mode108 Serial port modeTiming chart 109 Mode 1 baud rate MSM80C154S/83C154S/85C154HVS Mode OutlineMode 1 receive operation Mode 1 transmit operationMSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection Start Serr RXD Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0113 114 Mode 2 baud rate Mode OutlineMode 2 transmit operation Mode 2 receive operationMode 2 Uart error detection Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port Internal BUS Write Start TBB Sbuf TXD To Sbuf118 Mode 3 baud rate Mode 3 receive operation Mode 3 transmit operationMode 3 Uart error detection 122 123 Inhibit F E D C B a Input QHSHIFT/ Load Serial ClockRXD PX.X TXD RX.X TXDCLK Qhqg QF QE Qdqc QB QARXD TXD PX.X PX.X RXD TXDSHIFT/ Load Serial Clock 126Output PX.X Control RXD Input PX.X Control TXD127 42 lnput/output extension example timing chartMaster Slave MSM80C154S/83C154S/85C154HVS Multi-processor systemsTXD RXD 18 lnterrupt addresses InterruptEquivalent circuit 130Interrupt control ET1 19 lnterrupt enable register IE, 0A8H20 nterrupt priority register IP, 0B8H PX1Priority interrupt routine flow Clrea 21 Non-priority interrupt order of preference 22 TCON88H register External interrupt signal 0 and 1 level detectionTF1 TR1 TF0 IE1 IT1 IE0 IT0BUS Tcon Reset External interrupt signal 0 and 1 trigger detectionPage 139 Page 141 Page 143 Page 145 Idle mode Idle setting CPU Power DownXtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL Xtal TIMER, S-I/O Interrupt147 148 23 CPU pin details in idle mode149 Idle150 55IdlemodesettingtimeSoft power down mode PD setting 152 Mode equivalent circuitCPU Clock Pcon 87H Control Smod HPD RPD GF1Reset END PdresetPCON5RPD Pdreset 153154 TIMER0155 24 CPU pin details ALF=0 in soft power down mode PD156 Soft power down mode settingTime chart internal ROM mode Soft 158 25 CPU pin details ALF=1 in soft power down mode PD159 Down160 63SoftpowerdownmodesettingHard power down mode HPD setting Xtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL Hard power down162 163 26 CPU pin details ALF=0 in hard power down mode HPDMode 164165 166 27 CPU pin details ALF=1 in hard power down mode HPD167 168 68HardpowerdownmodesettingCancellation by CPU resetting Reset pin MSM80C154S/83C154S/85C154HVS By reset internal ROM mode170 171 172 173 By reset external ROM mode174 Mode by reset internal ROM mode175 Mode by reset external ROM modeSmod HPD RPD GF1 GF0 IDL 29 Power control register Pcon 87H177 IDLE, PD Mode Interrupt RestartINT 179 180 Internal ROM mode181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense 184 Restart from idle mode byOr 1 external ROM mode 185 Or 1 internal ROM mode186 External ROM modeInternal Specifications 188 Back up with hard power down modeBack 189190 INPUT/OUTPUT PortsPage Port 0 internal equivalent circuit OutlinePort WPO Modify 193Internal BUS Read Port 0 pin table 194Port Port 1 internal equivalent circuit 196Control Modify Port Read WP1 Internal BUS Read OFF 197OFF 198 On P3 On P2 Internal BUS Readoff N 199Port 1 pin table 200Port 1 CPU control pin table Port 2 internal equivalent circuit PC/DATADPH Port Read Modify WP2 Control PORT2 202WP3 Internal BUS Control Modify Read DataPort 3 pin table 204Port 3 CPU control pin function table INPUT/OUTPUT Ports Modify Port Read Internal BUS Power Down Iocon 0F8H206 INPUT/OUTPUT Ports 12 NPN transistor direct connection circuit CPU 1 OUTCPU 0 OUT 209One machine cycle instruction output timing Port Output TimingTwo machine cycle instruction output timing 16 Two machine cycle instruction port output time chartPort Data Manipulating Instructions 213 214 MSM80C154/83C154/85C154Electrical Characteristics Operational Ranges Absolute Maximum RatingsVCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85C DC CharacteristicsPort 0, ALE, Psen SSV IV CC218 219 DC CharacteristicsRepeated for specified output pins Repeated for specified input pinsMeasuring circuits Input logic for specified statusExternal Program Memory Access AC Characteristics External program memory read cycle 222ALE Psen Port InstrOutput External Data Memory Access AC CharacteristicsExternal data memory write cycle 224External data memory read cycle Output Data Setup to Clock Rising Edge TQVXH Machine Cycle ALE Shift Clock Output Data Input Data 226Input/output signal AC Characteristics Measuring ConditionsFloating Test PointXTAL1 External Clock Input Waveform Conditions Exterminal Oscillator SignalDescription of Instructions Page Description of Instructions Description of Instruction Symbols Instruction table List of InstructionsMSM80C154S/MSM83C154S Address in this description Simplified Description of InstructionsCLR a CPL a RL a RLC a RR a RRC a Swap a 235236 MOV XRLMOV Dptr 238CLR SetbMovc A, @A+PC 239240 Ljmp Interrupt Enable AjmpSjmp JMP @A+DPTRThen Else Cjne 242Then Else Djnz 243244 External RAM 245Movx A, @DPTR NOPAcall code address Absolute call within 2K bytes Detailed Description of MSM80C154S/MSM83C154S InstructionsRS1 ADD A, #data Add immediate data247 248 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address249 ADD A, Rr Add register250 MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory251 Addc A, #data Add carry plus immediate data to accumulator252 253 ADD A, Rr Add carry plus register to accumulator254 255 Ajmp code address Absolute jump within 2K byte256 257 ANL A, @Rr Logical and indirect address to accumulator258 259 ANL A, data address Logical and memory to accumulator260 261 ANL C,/bit address Logical and complement bit to carry flag262 263 ANL data address, a Logical and accumulator to memory264 LOC OBJ Source 265Testajmp TEST1 Compcjne @R1, #05H, Test266 Cjne A, #0AH, SS1 LOC OBJ Source 267SS1MOV R7, a Compcjne A, #0AH, SS1268 Cjne A, 50H, Next LOC OBJ Source 269Compcjne A, 50H, Next Callcall TestCompared data is not equal. If the compared data is equal 270Countinc R4 271272 MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator273 CLR C Clear carry flag274 MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit275 CPL a Complement accumulator276 MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag277 CPL bit address Complement bit278 MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator279 280 281 DEC a Decrement accumulator282 MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register283 DEC data address Decrement memoryAC F0 RS1 RS0 OV F1 MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by B284 285 Djnz R1, Loop LOC OBJ Source 286Loopadd A, R7 Countdjnz R1, Loop287 Countdjnz 57H, Loop 288Djnz 57H, Loop LOC OBJ Source 289 INC @Rr Increment indirect address290 MSM80C154S/83C154S/85C154HVS INC a Increment accumulator291 INC Dptr Increment data pointerRS1 RS0 PSW DPH DPL292 MSM80C154S/83C154S/85C154HVS INC Rr Increment register293 INC data address Increment memory294 ACA0 Entermov R4, 0A0H 295Bittsjb 34.3, Enter 296 297 298 Checkacall Addr 299Jmpcjc Carry Carryinc @R1Byte Description 300301 JNB bit address, code address Jump if bit is not setExitmov A, @R0 302Testjnb 37.3, Exit 303 JNC code address Jump if carry is not setExitmov B, ACC 304Testjnc Exit 305 JNZ code address Jump if accumulator is notJNZ Test LOC OBJ Source 306Checkjnz Test Testmov R3, a307 JZ code address Jump if accumulator is notJZ Empty LOC OBJ Source 308Emptyinc a Checkjz Empty309 Lcall code address Long call310 MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump6AH MOV @Rr, #data Move immediate data to indirect address311 6CH 312313 MOV @Rr, data address Move memory to indirect address314 315 MOV A, @Rr Move indirect address to accumulator316 317 MOV A, data address Move memory to accumulator318 DPH·DPL MOV DPTR, #data Move immediate data to data pointer319 320 321 MOV Rr, a Move accumulator to register5AH 322323 MOV bit address, C Move carry flag to bit324 325 MOV data address, @Rr Move indirect address to memory326 6BH MOV data address, Rr Move register to memory327 328 Movc A, @A+DPTR 329330 62CCH 331332 57AFH 333DPL DPH 334 335 MUL AB Multiply accumulator by B336 MSM80C154S/83C154S/85C154HVS NOP No operation337 ORL A, #data Logical or immediate data to accumulator338 339 ORL A, Rr Logical or register to accumulator340 341 ORL C, bit address Logical or bit to carry flag342 343 ORL data address, #data Logical or immediate data to memory344 345 POP data address Pop stack to memory346 347 RET Return from subroutine, non interrupt348 RS1 RS0 OV F1 P PSW RL a Rotate accumulator left349 350 351 RR a Rotate accumulator right352 353 Setb C Set carry flag354 MSM80C154S/83C154S/85C154HVS Setb bit address Set bit355 Sjmp code address Short jumpCheckrlc a 356Sjumpsjmp Check 357 358 359 Subb A, Rr Substract register from accumulator with borrow360 361 Swap a Exchange nibble in accumulator362 363 XCH A, Rr Exchange register with accumulator7AH 364365 366 367 368 369 370 371