Main
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CONTENTS
1. INTRODUCTION
2. SYSTEM CONFIGURATION
3. CONTROL
4. INTERNAL SPECIFICATIONS
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5. INPUT/OUTPUT PORTS
6. ELECTRICAL CHARACTERISTICS
7. DESCRIPTION OF INSTRUCTIONS
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1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline
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1.2 MSM80C154S/MSM83C154S Features
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1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
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2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
2.2 MSM80C154S/MSM83C154S pin layouts
Figure 2-2 MSM80C154S/MSM83C154S pin layout (top view)
Applicable Packages
2.2.1 MSM80C154S/MSM83C154S external dimensions
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2.2.2 MSM85C154HVS pin layout and external dimensions
2.3 MSM80C154S Block Diagram
2.4 MSM83C154S Block Diagram
2.5 MSM85C154HVS Block Diagram
2.6 Timing and Control
Figure 2-9 MSM80C154S/MSM83C154S fundamental timing
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2.6.3 MSM80C154S fundamental operation time charts
(2) MOVX A, @Rr
(1) External program memory read cycle timing chart
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(3) MOVX @Rr, A
(4) MOVX A, @DPTR
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(5) MOVX @DPTR, A
(6) MOV direct, PORT [0, 1, 2, 3] execution
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2.6.4 MSM83C154S fundamental operation time charts
(2) MOVX @Rr, A
(1) MOVX A, @Rr
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(3) MOVX A, @DPTR
(4) MOVX @DPTR, A
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(5) MOV direct, PORT [0, 1, 2, 3] execution
2.7 Instruction Register (IR) and Instruction Decoder (PLA)
2.8 Arithmetic Operation Section
2.9 Program Counter
2.10 Program Memory and External Data Memory
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Figure 2-27 DPTR external data memory access timing
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Figure 2-29 Register R0/R1 external data memory access timing
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3. CONTROL
3.1 Oscillators: XTAL1 XTAL2
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* Supply of 50% duty clock
3.2 CPU Resetting
Figure 3-5 Reset execution time chart (internal ROM mode)
CONTROL
Figure 3-6 Reset execution time chart (external ROM mode)
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Figure 3-7 Reset release time chart (internal ROM mode)
CONTROL
Figure 3-8 Reset release time chart (external ROM mode)
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3.3 EA (CPU Memory Separate)
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4. INTERNAL SPECIFICATIONS
4.1 Internal Data Memory (RAM) and Special Function Registers
Figure 4-1 Data memory and special function register layout
4.2 Internal Data Memory (RAM)
Figure 4-2 RAM layout diagram
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4.3 lnternal Data Memory (RAM) Operating Procedures
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4.4 Special Function Registers (TCON, SCON,.... ACC, B)
Table 4-6 List of special function registers
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4.4.2 Special function registers 4.4.2.1 Timer mode register (TMOD)
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4.4.2.2 Power control register (PCON)
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4.4.2.3 Timer control register (TCON)
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4.4.2.4 Serial port control register (SCON)
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4.4.2.5 Interrupt enable register (IE)
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4.4.2.6 Interrupt priority register (IP)
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4.4.2.7 Program status word register (PSW)
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4.4.2.8 I/O control register (IOCON)
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4.4.2.9 Timer 2 control register (T2CON)
4.5 Timer/Counters 0, 1 and 2 4.5.1 Outline
Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1
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4.6 Serial Port
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Table 4-15 SCON
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Figure 4-29 Serial port (mode 0) timing chart
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Figure 4-32 Serial port (mode 1) timing chart
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Figure 4-34 Serial port (mode 2) timing chart
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Figure 4-36 Serial port (mode 3) timing chart
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4.7 Interrupt
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4.8 CPU Power Down
Figure 4-53 ldle mode equivalent circuit
Table 4-23 CPU pin details in idle mode
Figure 4-54 Idle mode setting time chart (internal ROM mode)
Figure 4-55 Idle mode setting time chart (external ROM mode)
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Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD)
Figure 4-60 Soft power down mode setting time chart (internal ROM mode)
Figure 4-61 Soft power down mode setting time chart (external ROM mode)
Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD)
Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode)
Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode)
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Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD)
Figure 4-65 Hard power down mode setting time chart (internal ROM mode)
Figure 4-66 Hard power down mode setting time chart (external ROM mode)
Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD)
Figure 4-67 Hard power down mode setting and I/O floating time chart (internal ROM mode)
Figure 4-68 Hard power down mode setting andl/Of loating time chart (external ROM mode)
4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
Figure 4-69 Restart from idle mode by reset (internal ROM mode)
Figure 4-70 Restart from idle mode by reset (external ROM mode)
Figure 4-71 Restart from soft power mode by reset (internal ROM mode)
Figure 4-72 Restart from soft power mode by reset (external ROM mode)
Figure 4-73 Restart from hard power down mode by reset (internal ROM mode)
Figure 4-74 Restart from hard power down mode by reset (external ROM mode)
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Figure 4-76 Restart from idle mode by interrupt INT0 or 1 (internal ROM mode)
Figure 4-77 Restart from idle mode by interrupt INT0 or 1 (external ROM mode)
Figure 4-78 Restart from soft power down mode by Interrupt INT0 or 1 (internal ROM mode)
Figure 4-79 Restart from soft power down mode by interrupt INT0 or 1 (external ROM mode)
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Figure 4-81 Restart from idle mode by INT0 or 1 (internal ROM mode)
Figure 4-82 Restart from idle mode by INT0 or 1 (external ROM mode)
Figure 4-83 Restart from soft power down mode by INT0 or 1 (internal ROM mode)
Figure 4-84 Restart from soft power down mode by INT0 or 1 (external ROM mode)
4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode
Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode
Figure 4-85-2/2 MSM80C154S/83C154S battery back up with hard power down mode
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5. INPUT/OUTPUT PORTS
5.1 Outline
5.2 Port 0
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5.3 Port 1
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Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart
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5.4 Port 2
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5.5 Port 3
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5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD)
Figure 5-11 Control circuit for ports 0, 1, 2, 3 by lOCON
5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2, and 3
5.8 100 kohm Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1, 2, and 3
5.9 Precautions When Driving External Transistors by Ouasi-bidirectional Port Output Signals
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5.10 Port Output Timing
Figure 5-15 One machine cycle instruction port output time chart
1) One machine cycle instruction output timing
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2) Two machine cycle instruction output timing
Figure 5-16 Two machine cycle instruction port output time chart
5.11 Port Data Manipulating Instructions
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6. ELECTRICAL CHARACTERISTICS
Supply Voltage VCC (V)
6.1 Absolute Maximum Ratings
6.2 Operational Ranges
t ( m s) f
6.3 DC Characteristics 1
(VCC=4.0 to 6.0V,VSS=0V, Ta=40C to +85C)
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DC Characteristics 2
Maximum power supply current idle mode ICC (mA)
Maximum power supply current normal operation ICC (mA)
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Measuring circuits
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6.4 External Program Memory Access AC Characteristics
*1 The variable check is from 0 to 24 MHz when the external check is used.
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6.5 External Data Memory Access AC Characteristics
*1 The variable check is from 0 to 24 MHz when the external check is used. *2 For 2.2VCC<4 V
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6.6 Serial Port (I/O Extension Mode) AC Characteristics
VCC=2.2 to.0V, VSS=0V, Ta=40C to 85C
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6.7 AC Characteristics Measuring Conditions
1. Input/output signal
2. Floating
6.8 XTAL1 External Clock Input Waveform Conditions
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7. DESCRIPTION OF INSTRUCTIONS
7.1 Outline
7.2 Description of Instruction Symbols
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7.3 List of Instructions
MSM80C154S/MSM83C154S instruction table
7.4 Simplified Description of Instructions
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Note that data address is represented as direct address in this description.
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7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions
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2. ADD A, #data (Add immediate data)
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3. ADD A, @Rr (Add indirect address)
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4. ADD A, Rr (Add register)
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5. ADD A, data address (Add memory)
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6. ADDC A, #data (Add carry plus immediate data to accumulator)
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7. ADDC A, @Rr (Add carry plus indirect address to accumulator)
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8. ADD A, Rr (Add carry plus register to accumulator)
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9. ADDC A, data address (Add carry plus memory to accumulator)
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10. AJMP code address (Absolute jump within 2K byte page)
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11. ANL A, #data (Logical AND immediate data to accumulator)
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12. ANL A, @Rr (Logical AND indirect address to accumulator)
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13. ANL A, Rr (Logical AND register to accumulator)
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14. ANL A, data address (Logical AND memory to accumulator)
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15. ANL C, bit address (Logical AND bit to carry flag)
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16. ANL C,/bit address (Logical AND complement bit to carry flag)
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17. ANL data address, #data (Logical AND immediate data to memory)
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18. ANL data address, A (Logical AND accumulator to memory)
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19. CJNE @Rr, #data, code address (Compare indirect address to immediate data, jump if not equal)
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20. CJNE A, #data, code address (Compare immediate data to accumulator, jump if not equal)
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21. CJNE A, data address, code address (Compare memory to accumulator, jump if not equal)
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22. CJNE Rr, #data, code address (Compare immediate data to register, jump if not equal)
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23. CLR A (Clear accumulator)
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24. CLR C (Clear carry flag)
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25. CLR bit address (Clear bit)
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26. CPL A (Complement accumulator)
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27. CPL C (Complement carry flag)
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28. CPL bit address (Complement bit)
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29. DA A (Decimal adjust accumulator)
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30. DEC @Rr (Decrement indirect address)
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31. DEC A (Decrement accumulator)
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32. DEC Rr (Decrement register)
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33. DEC data address (Decrement memory)
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34. DIV AB (Divide accumulator by B)
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35. DJNZ Rr, code address (Decrement register, and jump if not zero)
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36. DJNZ data address, code address (Decrement memory, and jump if not zero)
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37. INC @Rr (Increment indirect address)
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38. INC A (Increment accumulator)
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39. INC DPTR (Increment data pointer)
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40. INC Rr (Increment register)
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41. INC data address (Increment memory)
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42. JB bit address, code address (Jump if bit is set)
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43. JBC bit address, code address (Jump and clear if bit is set)
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44. JC code address (Jump if carry is set)
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45. JMP @A + DPTR (Jump to sum of accumulator and data pointer)
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46. JNB bit address, code address (Jump if bit is not set)
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47. JNC code address (Jump if carry is not set)
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48. JNZ code address (Jump if accumulator is not 0)
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49. JZ code address (Jump if accumulator is not 0)
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50. LCALL code address (Long call)
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51. LJMP code address (Long jump)
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52. MOV @Rr, #data (Move immediate data to indirect address)
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53. MOV @Rr, A (Move accumulator to indirect address)
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54. MOV @Rr, data address (Move memory to indirect address)
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55. MOV A, #data (Move immediate data to accumulator)
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56. MOV A, @Rr (Move indirect address to accumulator)
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57. MOV A, Rr (Move register to accumulator)
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58. MOV A, data address (Move memory to accumulator)
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59. MOV C, bit address (Move bit to carry flag)
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60. MOV DPTR, #data (Move immediate data to data pointer)
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61. MOV Rr, #data (Move immediate data to register)
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62. MOV Rr, A (Move accumulator to register)
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63. MOV Rr, data address (Move memory to register)
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64. MOV bit address, C (Move carry flag to bit)
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65. MOV data address, #data (Move immediate data to memory)
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66. MOV data address, @Rr (Move indirect address to memory)
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67. MOV data address, A (Move accumulator to memory)
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68. MOV data address, Rr (Move register to memory)
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69. MOV data address 1, data address 2 (Move memory to memory)
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70. MOVC A, @A + DPTR (Move code memory offset from data pointer to accumulator)
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71. MOVC A, @A + PC (Move code memory offset from program counter to accumulator)
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72. MOVX @DPTR, A (Move accumulator to external memory addressed by data pointer)
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73. MOVX @Rr, A (Move accumulator to external memory addressed by register)
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74. MOVX A, @DPTR (Move external memory addressed by data pointer to accumulator)
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75. MOVX A, @Rr (Move external memory addressed by register to accumulator)
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76. MUL AB (Multiply accumulator by B)
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77. NOP (No operation)
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78. ORL A, #data (Logical OR immediate data to accumulator)
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79. ORL A, @Rr (Logical OR indirect address to accumulator)
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80. ORL A, Rr (Logical OR register to accumulator)
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81. ORL A, data address (Logical OR memory to accumulator)
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82. ORL C, bit address (Logical OR bit to carry flag)
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83. ORL C,/bit address (Logical OR complement of bit to carry flag)
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84. ORL data address, #data (Logical OR immediate data to memory)
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85. ORL data address, A (Logical OR accumulator to memory)
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86. POP data address (Pop stack to memory)
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87. PUSH data address (Push memory onto stack)
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88. RET (Return from subroutine, non interrupt)
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89. RETI (Return from interrupt routine)
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90. RL A (Rotate accumulator left)
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91. RLC A (Rotate accumulator and carry flag left)
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92. RR A (Rotate accumulator right)
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93. RRC A (Rotate accumulator and carry flag right)
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94. SETB C (Set carry flag)
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95. SETB bit address (Set bit)
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96. SJMP code address (Short jump)
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97. SUBB A, #data (Substract immediate data from accumulator with borrow)
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98. SUBB A, @Rr (Substract indirect address from accumulator with borrow)
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99. SUBB A, Rr (Substract register from accumulator with borrow)
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100. SUBB A, data address (Substract memory from accumulator with borrow)
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101. SWAP A (Exchange nibble in accumulator)
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102. XCH A, @Rr (Exchange indirect address with accumulator)
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103. XCH A, Rr (Exchange register with accumulator)
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104. XCH A, data address (Exchange memory with accumulator)
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105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator)
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106. XRL A, #data (Logical exclusive OR immediate data to accumulator)
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107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator)
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108. XRL A, Rr (Logical exclusive OR register to accumulator)
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109. XRL A, data address (Logical exclusive OR memory to accumulator)
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110. XRL data address, #data (Logical exclusive OR immediate data to memory)
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111. XRL data address, A (Logical exclusive OR accumulator to memory)
