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Sonic Alert msm80154s, msm83c154s, msm85c154hvs CPU Resetting, Outline, CPU Reset Control

Models: msm83c154s msm85c154hvs msm80154s

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Page 52

CONTROL

3.2 CPU Resetting

3.2.1 Outline

If a reset signal (kept at “1” level for at least ∝1sec) is applied to the RESET pin when the correct voltage (in respect to the various specifications) is applied to the MSM80C154S/ MSM83C154S VCC pin, a reset signal is stored in the CPU even if the XTAL1·2 oscillators have been stopped.

The internally stored reset signal is used in direct initialization (setting to “1”) of ports 0, 1, 2, and 3. All of the special function registers are then initialized (set to “0”) two machine cycles after the XTAL1·2 oscillator commences regular operation.

When the reset is released, instruction execution is started in the third machine cycle if the reset signal is changed from “1” level to “0” level before the M1·S1 signal leading edge, and in the fifth machine cycle if the reset signal is changed from “1” to “0” after the leading edge. The reset circuit block diagram is shown in Figure 3-4, the reset start time charts in Figures 3-5 and 3-6, and the reset release time charts in Figures 3-7 and 3-8.

VCC

+

–RESET

R=40K•• Ω

IN CPU RESET CONTROL

Figure 3-4 MSM80C154S/MSM83C154S reset circuit block diagram

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Image 52

Sonic Alert msm80154s, msm83c154s, msm85c154hvs user manual CPU Resetting, Outline, CPU Reset Control

Contents

MSM80C154S MSM83C154S Page Contents Reset Schmitt trigger circuit CPU internal status by reset 2.5.22.5.3 2.5.4Power down mode 3.4.2 T2EXtimer/counter 2 external flag input detector3.1 Special function registers for serial port 101 2.1Multi-processor systems 128 129140 142KW Pull-Up Resistance Setting for Quasi-bidirectional Input 207208 210Introduction Page Introduction MSM80C154S/MSM83C154S/MSM85C154HVS OutlineMSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154S/MSM83C154S pin layouts MSM80C154SRS/MSM83C154SRSMSM80C154S/MSM83C154S pin layout top view Applicable Packages 1 MSM80C154S/MSM83C154S external dimensions MSM80C154S/MSM83C154S external dimensionsMSM80C154STS/MSM83C154STS 2 MSM85C154HVS pin layout and external dimensions MSM85C154HVS pin layout and external dimensionsSignal TIMER/COUNTER 0&1 Interrupt Serial IOSpecial Function Register AddressROM Special DPL PLA Register AddressSense AMP TH1 TL1 TH0 TL0 Tmod TconSignal DPH T2CON TL2 TH2 AMP ACC TR2 TR1Address Decoder TH1 TL1 TH0 TL0Timing and Control Outline of MSM80C154S/MSM83C154S timingTiming 9MSM80C154S/MSM83C154SMajor synchronizing signals Movx A, @Rr External program memory read cycle timing chartXTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT 12 MSM80C154S Movx @Rr, a execution 13 MSM80C154S Movx A, @DPTR executionXTAL1 ALE Psen MOV direct, Port 0, 1, 2, 3 executionPIN Data CPU Data PIN Data Stable Sampled 4 MSM83C154S fundamental operation time charts 16 MSM83C154S Movx A, @Rr execution18 MSM83C154S Movx A, @DPTR execution 19 MSM83C154S Movx @DPTR, a executionPIN Data PIN Data Stable CPU Data Sampled 20 MSM83C154S MOV direct, PORT0, 1, 2, 3 executionInstruction Register IR and Instruction Decoder PLA AIRPLA Wair PLA WIRArithmetic Operation Section PSW0D0H CY AC F0 RS1 RS0 OV F1 PProgram Counter CPU Internal Data BUSProgram Memory and External Data Memory 24 MSM80C154S/MSM83C154S program areaALE Latch System Configuration Dptr XTAL1 ALE Psen Page MSM80C154S/MSM83C154S By register R0 or R1Data Control Page Crystal resonator connection diagram Oscillators XTAL1 XTAL2Supply of 50% duty clock Clock XTAL2CPU Reset Control CPU ResettingOutline ROM mode 5ResetexecutionChart Chart XTAL1 Psen ALE MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuit Reset Schmitt trigger gate detector time chartDenotes direct resetting even if XTAL1·2 has stopped CPU internal status by resetMSM80C154S/MSM83C154S reset internal status EA CPU Memory Separate Internal Specifications Page Internal Specifications Internal Data Memory RAM and Special Function RegistersData memory and special function register layout Internal Data Memory RAM Internal data memory RAMRAM layout diagram Internal data memory registers R0 thru R7 Program status word PSWRS0 User Data RAMMSM80C154S/83C154S/85C154HVS Stack Stack storage layoutPC5 PC1Lnternal Data Memory RAM Operating Procedures Internal data memory indirect addressingDEC Rr bit arrangement Register designation table Internal data memory 1-bit data designation CLR bit address bit arrangementBit designation table Addressing combination table2AH 2BH 2EHSpecial Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon SCON.6 SM1 SM0 Mode MSB LSB SconSM0 SM1 SM2 REN TB8 RB8 SCON.0Interrupt enable register IE MSB LSBET2 ET1 EX1 ET0 EX0 ET2PCT PT2 PT1 PX1 PT0 PX0 MSM80C154S/83C154S/85C154HVS Interrupt priority register IPPCT Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon Timer 2 control register T2CON TF2 EXF2EXEN2 TF2Timer/Counters 0, 1 and 2 4.5.1 Outline Timer/counters 0 and 1 4.5.2.1 OutlineTimer/counter 0 and 1 counting control Timer control register Tcon 88HCircuit for timer/counters 0 Overall clock input controlTimer mode register Tmod 89H Timer External clock detector circuit for timer/counters 0PD & HPD Counting control of timer/counters 0 and 1 by INT pin Detector circuit operational time chartTimer Gate TR0 INT0 RUN Stop TR1 INT1 Timer ClockDetector Timer Counter 11 Timer mode register Tmod 89HMode T0 PIN Detector Port TR0 Gate INT0 PIN Data Detector TF0 TL0 TH0 5BITS 8BITST1 PIN Detector Port TR1 Gate INT1 PIN Data Latch Detector TF1 TL1 TH1 5BITS 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode Detector TF0 TH0 8BITSLatch Detector TF1 TH1 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode T0 PIN Detector Port TF0 8BITS TR0 GateINT0 PIN 8BITS Data Reload Data XtalDetector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN Data Latch XtalTL0 8BITS Detector TF1 TH0 C 8BITS2.5.6 32-bit timer mode T0 PIN DetectorIocon 0F8H Serr IZCTimer Reset 19 T0, T1 external clock detector circuitInternal Specifications 12 Timer 2 control register T2CON 0C8H Mode 1 or 3 has been setBit is 0, and valid when Must be reset to 0 by software Timer/counter 2 operation modes3.3.1 16-bit auto reload mode To 0 by software3.3.2 16-bit capture mode TR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 InterruptRCLK=0 TCLK=0 TL2 TH2 BIT3.3.3 16-bit baud rate generator mode 21 Timer/counter 2 16-bit capture mode circuitBaud Reset Timer Counter Clock 3.4.2 T2EX timer/counter 2 external flag input detectorReset Timer Counter T2EX Timer/counter detector circuit Detector PD & HPD O ClockSerial Port RX Control Input Shift Register 100Sbuf R Internal Specifications 102 15 SconSbuf serial port buffer register TclkRclk 16 Serial port operation modesMSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 transmit operation Mode 0 baud rateMode 0 receive operation Port mode 107Timing chart Serial port mode108 109 MSM80C154S/83C154S/85C154HVS Mode Outline Mode 1 baud rateMode 1 transmit operation Mode 1 receive operationMSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection 113 Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0Start Serr RXD 114 Mode Outline Mode 2 baud rateMode 2 transmit operation Mode 2 receive operationMode 2 Uart error detection Internal BUS Write Start TBB Sbuf TXD To Sbuf Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port118 Mode 3 baud rate Mode 3 transmit operation Mode 3 receive operationMode 3 Uart error detection 122 123 QHSHIFT/ Load Serial Clock Inhibit F E D C B a InputRXD PX.X TXD RX.X TXDQhqg QF QE Qdqc QB QA CLKRXD TXD PX.X PX.X RXD TXD126 SHIFT/ Load Serial ClockOutput PX.X Control RXD Input PX.X Control TXD42 lnput/output extension example timing chart 127TXD RXD MSM80C154S/83C154S/85C154HVS Multi-processor systemsMaster Slave Interrupt 18 lnterrupt addressesInterrupt control 130Equivalent circuit 19 lnterrupt enable register IE, 0A8H ET1PX1 20 nterrupt priority register IP, 0B8HPriority interrupt routine flow Clrea 21 Non-priority interrupt order of preference External interrupt signal 0 and 1 level detection 22 TCON88H registerTF1 TR1 TF0 IE1 IT1 IE0 IT0External interrupt signal 0 and 1 trigger detection BUS Tcon ResetPage 139 Page 141 Page 143 Page 145 CPU Power Down Idle mode Idle setting147 Xtal TIMER, S-I/O InterruptXtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL 23 CPU pin details in idle mode 148Idle 14955Idlemodesettingtime 150Soft power down mode PD setting Mode equivalent circuit 152CPU Clock Pcon 87H Control Smod HPD RPD GF1Pdreset Reset ENDPCON5RPD Pdreset 153TIMER0 15424 CPU pin details ALF=0 in soft power down mode PD 155Time chart internal ROM mode Soft power down mode setting156 Soft 25 CPU pin details ALF=1 in soft power down mode PD 158Down 15963Softpowerdownmodesetting 160Hard power down mode HPD setting 162 Hard power downXtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL 26 CPU pin details ALF=0 in hard power down mode HPD 163164 Mode165 27 CPU pin details ALF=1 in hard power down mode HPD 166167 68Hardpowerdownmodesetting 168Cancellation by CPU resetting Reset pin 170 By reset internal ROM modeMSM80C154S/83C154S/85C154HVS 171 172 By reset external ROM mode 173Mode by reset internal ROM mode 174Mode by reset external ROM mode 17529 Power control register Pcon 87H Smod HPD RPD GF1 GF0 IDLIDLE, PD Mode Interrupt Restart 177INT 179 Internal ROM mode 180181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense Or 1 external ROM mode Restart from idle mode by184 Or 1 internal ROM mode 185External ROM mode 186Internal Specifications Back up with hard power down mode 188189 BackINPUT/OUTPUT Ports 190Page Port OutlinePort 0 internal equivalent circuit Internal BUS Read 193WPO Modify 194 Port 0 pin tablePort Control Modify Port Read WP1 196Port 1 internal equivalent circuit OFF 197Internal BUS Read OFF 198 199 On P3 On P2 Internal BUS Readoff NPort 1 CPU control pin table 200Port 1 pin table DPH Port Read Modify WP2 Control PC/DATAPort 2 internal equivalent circuit 202 PORT2Internal BUS Control Modify Read Data WP3Port 3 CPU control pin function table 204Port 3 pin table INPUT/OUTPUT Ports 206 Power Down Iocon 0F8HModify Port Read Internal BUS INPUT/OUTPUT Ports CPU 1 OUT 12 NPN transistor direct connection circuit209 CPU 0 OUTPort Output Timing One machine cycle instruction output timing16 Two machine cycle instruction port output time chart Two machine cycle instruction output timingPort Data Manipulating Instructions 213 MSM80C154/83C154/85C154 214Electrical Characteristics Absolute Maximum Ratings Operational RangesDC Characteristics VCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85CPort 0, ALE, Psen SSV IV CC218 DC Characteristics 219Repeated for specified input pins Repeated for specified output pinsMeasuring circuits Input logic for specified statusExternal Program Memory Access AC Characteristics 222 External program memory read cycleALE Psen Port InstrExternal Data Memory Access AC Characteristics OutputExternal data memory read cycle 224External data memory write cycle Output Data Setup to Clock Rising Edge TQVXH 226 Machine Cycle ALE Shift Clock Output Data Input DataAC Characteristics Measuring Conditions Input/output signalFloating Test PointExterminal Oscillator Signal XTAL1 External Clock Input Waveform ConditionsDescription of Instructions Page Description of Instructions Description of Instruction Symbols MSM80C154S/MSM83C154S List of InstructionsInstruction table Simplified Description of Instructions Address in this description235 CLR a CPL a RL a RLC a RR a RRC a Swap a236 XRL MOV238 MOV DptrCLR Setb239 Movc A, @A+PC240 Interrupt Enable Ajmp LjmpSjmp JMP @A+DPTR242 Then Else Cjne243 Then Else Djnz244 245 External RAMMovx A, @DPTR NOPDetailed Description of MSM80C154S/MSM83C154S Instructions Acall code address Absolute call within 2K bytes247 ADD A, #data Add immediate dataRS1 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address 248ADD A, Rr Add register 249MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory 250Addc A, #data Add carry plus immediate data to accumulator 251252 ADD A, Rr Add carry plus register to accumulator 253254 Ajmp code address Absolute jump within 2K byte 255256 ANL A, @Rr Logical and indirect address to accumulator 257258 ANL A, data address Logical and memory to accumulator 259260 ANL C,/bit address Logical and complement bit to carry flag 261262 ANL data address, a Logical and accumulator to memory 263264 265 LOC OBJ SourceTestajmp TEST1 Compcjne @R1, #05H, Test266 267 Cjne A, #0AH, SS1 LOC OBJ SourceSS1MOV R7, a Compcjne A, #0AH, SS1268 269 Cjne A, 50H, Next LOC OBJ SourceCompcjne A, 50H, Next Callcall Test270 Compared data is not equal. If the compared data is equal271 Countinc R4MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator 272CLR C Clear carry flag 273MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit 274CPL a Complement accumulator 275MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag 276CPL bit address Complement bit 277MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator 278279 280 DEC a Decrement accumulator 281MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register 282DEC data address Decrement memory 283284 MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by BAC F0 RS1 RS0 OV F1 285 286 Djnz R1, Loop LOC OBJ SourceLoopadd A, R7 Countdjnz R1, Loop287 Djnz 57H, Loop LOC OBJ Source 288Countdjnz 57H, Loop INC @Rr Increment indirect address 289MSM80C154S/83C154S/85C154HVS INC a Increment accumulator 290INC Dptr Increment data pointer 291RS1 RS0 PSW DPH DPLMSM80C154S/83C154S/85C154HVS INC Rr Increment register 292INC data address Increment memory 293294 Bittsjb 34.3, Enter 295ACA0 Entermov R4, 0A0H 296 297 298 299 Checkacall AddrJmpcjc Carry Carryinc @R1300 Byte DescriptionJNB bit address, code address Jump if bit is not set 301Testjnb 37.3, Exit 302Exitmov A, @R0 JNC code address Jump if carry is not set 303Testjnc Exit 304Exitmov B, ACC JNZ code address Jump if accumulator is not 305306 JNZ Test LOC OBJ SourceCheckjnz Test Testmov R3, aJZ code address Jump if accumulator is not 307308 JZ Empty LOC OBJ SourceEmptyinc a Checkjz EmptyLcall code address Long call 309MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump 310311 MOV @Rr, #data Move immediate data to indirect address6AH 312 6CHMOV @Rr, data address Move memory to indirect address 313314 MOV A, @Rr Move indirect address to accumulator 315316 MOV A, data address Move memory to accumulator 317318 319 MOV DPTR, #data Move immediate data to data pointerDPH·DPL 320 MOV Rr, a Move accumulator to register 321322 5AHMOV bit address, C Move carry flag to bit 323324 MOV data address, @Rr Move indirect address to memory 325326 327 MOV data address, Rr Move register to memory6BH 328 329 Movc A, @A+DPTR330 331 62CCH332 DPL DPH 33357AFH 334 MUL AB Multiply accumulator by B 335MSM80C154S/83C154S/85C154HVS NOP No operation 336ORL A, #data Logical or immediate data to accumulator 337338 ORL A, Rr Logical or register to accumulator 339340 ORL C, bit address Logical or bit to carry flag 341342 ORL data address, #data Logical or immediate data to memory 343344 POP data address Pop stack to memory 345346 RET Return from subroutine, non interrupt 347348 349 RL a Rotate accumulator leftRS1 RS0 OV F1 P PSW 350 RR a Rotate accumulator right 351352 Setb C Set carry flag 353MSM80C154S/83C154S/85C154HVS Setb bit address Set bit 354Sjmp code address Short jump 355Sjumpsjmp Check 356Checkrlc a 357 358 Subb A, Rr Substract register from accumulator with borrow 359360 Swap a Exchange nibble in accumulator 361362 XCH A, Rr Exchange register with accumulator 363364 7AH365 366 367 368 369 370 371