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Sonic Alert msm83c154s, msm80154s, msm85c154hvs user manual Major synchronizing signals

Models: msm83c154s msm85c154hvs msm80154s

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SYSTEM CONFIGURATION

2.6.2 Major synchronizing signals

(1)ALE (Address Latch Enable)

The ALE signal is used as a clock signal where the address signals 0 thru 7 output from CPU port 0 can be latched externally when external program or external data memory (RAM) is used.

Although two ALE signal outputs are obtained in a single machine cycle during normal operations, no output is obtained during output of the RD/WR signal when an external memory instruction (MOVX...... ) is executed.

(2)PSEN (Program Store Enable)

The PSEN output signal is generated during execution of an external program. The output is obtained when an instruction or data is fetched.

The PSEN signal is valid when at “0” level, and external program data is enabled when in this valid state.

Although two PSEN signal outputs are obtained in a single machine cycle during normal operations, no output is obtained during output of the RD/WR signal when an external data memory instruction (MOVX...... ) is executed.

(3)WR (Write Strobe)

The WR output signal is obtained when an external data memory instruction (MOVX @Rr, A or MOVX @ DPTR, A) is executed.

CPU port 0 output data is written in the external RAM when the WR signal is at “0” level.

(4)RD (Read Strobe)

The RD output signal is obtained when an external data memory instruction (MOVX A, @ Rr or MOVX A, @ DPTR) is executed.

The external RAM is enabled and output data is passed to CPU port 0 when the RD signal is at “0” level.

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Sonic Alert msm83c154s, msm80154s, msm85c154hvs user manual Major synchronizing signals

Contents

MSM80C154S MSM83C154S Page Contents 2.5.3 Reset Schmitt trigger circuit CPU internal status by reset2.5.2 2.5.43.1 Power down mode3.4.2 T2EXtimer/counter 2 external flag input detector Special function registers for serial port 101 2.1140 Multi-processor systems 128129 142208 KW Pull-Up Resistance Setting for Quasi-bidirectional Input207 210Introduction Page Introduction MSM80C154S/MSM83C154S/MSM85C154HVS OutlineMSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154S/MSM83C154S pin layouts MSM80C154SRS/MSM83C154SRSMSM80C154S/MSM83C154S pin layout top view Applicable Packages 1 MSM80C154S/MSM83C154S external dimensions MSM80C154S/MSM83C154S external dimensionsMSM80C154STS/MSM83C154STS 2 MSM85C154HVS pin layout and external dimensions MSM85C154HVS pin layout and external dimensionsSpecial Function SignalTIMER/COUNTER 0&1 Interrupt Serial IO Register AddressSense AMP ROM SpecialDPL PLA Register Address TH1 TL1 TH0 TL0 Tmod TconAddress Decoder Signal DPHT2CON TL2 TH2 AMP ACC TR2 TR1 TH1 TL1 TH0 TL0Timing and Control Outline of MSM80C154S/MSM83C154S timingTiming 9MSM80C154S/MSM83C154SMajor synchronizing signals External program memory read cycle timing chart Movx A, @RrXTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT 12 MSM80C154S Movx @Rr, a execution 13 MSM80C154S Movx A, @DPTR executionMOV direct, Port 0, 1, 2, 3 execution XTAL1 ALE PsenPIN Data CPU Data PIN Data Stable Sampled 4 MSM83C154S fundamental operation time charts 16 MSM83C154S Movx A, @Rr execution18 MSM83C154S Movx A, @DPTR execution 19 MSM83C154S Movx @DPTR, a executionPIN Data PIN Data Stable CPU Data Sampled 20 MSM83C154S MOV direct, PORT0, 1, 2, 3 executionPLA Wair Instruction Register IR and Instruction Decoder PLAAIR PLA WIRArithmetic Operation Section PSW0D0H CY AC F0 RS1 RS0 OV F1 PProgram Counter CPU Internal Data BUSProgram Memory and External Data Memory 24 MSM80C154S/MSM83C154S program areaALE Latch System Configuration Dptr XTAL1 ALE Psen Page MSM80C154S/MSM83C154S By register R0 or R1Data Control Page Crystal resonator connection diagram Oscillators XTAL1 XTAL2Supply of 50% duty clock Clock XTAL2CPU Resetting CPU Reset ControlOutline ROM mode 5ResetexecutionChart Chart XTAL1 Psen ALE MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuit Reset Schmitt trigger gate detector time chartCPU internal status by reset Denotes direct resetting even if XTAL1·2 has stoppedMSM80C154S/MSM83C154S reset internal status EA CPU Memory Separate Internal Specifications Page Internal Specifications Internal Data Memory RAM and Special Function RegistersData memory and special function register layout Internal Data Memory RAM Internal data memory RAMRAM layout diagram RS0 Internal data memory registers R0 thru R7Program status word PSW User Data RAMPC5 MSM80C154S/83C154S/85C154HVS StackStack storage layout PC1Lnternal Data Memory RAM Operating Procedures Internal data memory indirect addressingDEC Rr bit arrangement Register designation table Internal data memory 1-bit data designation CLR bit address bit arrangement2AH 2BH Bit designation tableAddressing combination table 2EHSpecial Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon SM0 SM1 SM2 REN TB8 RB8 SCON.6 SM1 SM0 ModeMSB LSB Scon SCON.0ET2 ET1 EX1 ET0 EX0 Interrupt enable register IEMSB LSB ET2MSM80C154S/83C154S/85C154HVS Interrupt priority register IP PCT PT2 PT1 PX1 PT0 PX0PCT Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon EXEN2 Timer 2 control register T2CONTF2 EXF2 TF2Timer/counter 0 and 1 counting control Timer/Counters 0, 1 and 2 4.5.1 OutlineTimer/counters 0 and 1 4.5.2.1 Outline Timer control register Tcon 88HCircuit for timer/counters 0 Overall clock input controlTimer mode register Tmod 89H External clock detector circuit for timer/counters 0 TimerPD & HPD Counting control of timer/counters 0 and 1 by INT pin Detector circuit operational time chartTimer Clock Timer Gate TR0 INT0 RUN Stop TR1 INT1Detector 11 Timer mode register Tmod 89H Timer CounterMode T1 PIN Detector Port TR1 Gate INT1 PIN Data T0 PIN Detector Port TR0 Gate INT0 PIN DataDetector TF0 TL0 TH0 5BITS 8BITS Latch Detector TF1 TL1 TH1 5BITS 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode Latch Detector TF1 Detector TF0TH0 8BITS TH1 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode INT0 PIN 8BITS Data T0 PIN Detector Port TF08BITS TR0 Gate Reload Data XtalTL0 8BITS Detector TF1 Detector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN DataLatch Xtal TH0 C 8BITSIocon 0F8H 2.5.6 32-bit timer modeT0 PIN Detector Serr IZCTimer Reset 19 T0, T1 external clock detector circuitInternal Specifications Mode 1 or 3 has been set 12 Timer 2 control register T2CON 0C8HBit is 0, and valid when 3.3.1 16-bit auto reload mode Must be reset to 0 by softwareTimer/counter 2 operation modes To 0 by softwareRCLK=0 TCLK=0 3.3.2 16-bit capture modeTR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 Interrupt TL2 TH2 BIT3.3.3 16-bit baud rate generator mode 21 Timer/counter 2 16-bit capture mode circuitBaud 3.4.2 T2EX timer/counter 2 external flag input detector Reset Timer Counter ClockReset Timer Counter T2EX Timer/counter detector circuit Detector PD & HPD O ClockSerial Port 100 RX Control Input Shift RegisterSbuf R Internal Specifications 102 15 SconRclk Sbuf serial port buffer registerTclk 16 Serial port operation modesMSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 baud rate Mode 0 transmit operationMode 0 receive operation Port mode 107Serial port mode Timing chart108 109 MSM80C154S/83C154S/85C154HVS Mode Outline Mode 1 baud rateMode 1 transmit operation Mode 1 receive operationMSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0 113Start Serr RXD 114 Mode 2 transmit operation Mode OutlineMode 2 baud rate Mode 2 receive operationMode 2 Uart error detection Internal BUS Write Start TBB Sbuf TXD To Sbuf Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port118 Mode 3 baud rate Mode 3 transmit operation Mode 3 receive operationMode 3 Uart error detection 122 123 RXD PX.X TXD QHSHIFT/ Load Serial ClockInhibit F E D C B a Input RX.X TXDRXD TXD PX.X Qhqg QF QE Qdqc QB QACLK PX.X RXD TXDOutput PX.X Control 126SHIFT/ Load Serial Clock RXD Input PX.X Control TXD42 lnput/output extension example timing chart 127MSM80C154S/83C154S/85C154HVS Multi-processor systems TXD RXDMaster Slave Interrupt 18 lnterrupt addresses130 Interrupt controlEquivalent circuit 19 lnterrupt enable register IE, 0A8H ET1PX1 20 nterrupt priority register IP, 0B8HPriority interrupt routine flow Clrea 21 Non-priority interrupt order of preference TF1 TR1 TF0 External interrupt signal 0 and 1 level detection22 TCON88H register IE1 IT1 IE0 IT0External interrupt signal 0 and 1 trigger detection BUS Tcon ResetPage 139 Page 141 Page 143 Page 145 CPU Power Down Idle mode Idle settingXtal TIMER, S-I/O Interrupt 147Xtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL 23 CPU pin details in idle mode 148Idle 14955Idlemodesettingtime 150Soft power down mode PD setting CPU Clock Mode equivalent circuit152 Pcon 87H Control Smod HPD RPD GF1PCON5RPD Pdreset PdresetReset END 153TIMER0 15424 CPU pin details ALF=0 in soft power down mode PD 155Soft power down mode setting Time chart internal ROM mode156 Soft 25 CPU pin details ALF=1 in soft power down mode PD 158Down 15963Softpowerdownmodesetting 160Hard power down mode HPD setting Hard power down 162Xtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL 26 CPU pin details ALF=0 in hard power down mode HPD 163164 Mode165 27 CPU pin details ALF=1 in hard power down mode HPD 166167 68Hardpowerdownmodesetting 168Cancellation by CPU resetting Reset pin By reset internal ROM mode 170MSM80C154S/83C154S/85C154HVS 171 172 By reset external ROM mode 173Mode by reset internal ROM mode 174Mode by reset external ROM mode 17529 Power control register Pcon 87H Smod HPD RPD GF1 GF0 IDLIDLE, PD Mode Interrupt Restart 177INT 179 Internal ROM mode 180181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense Restart from idle mode by Or 1 external ROM mode184 Or 1 internal ROM mode 185External ROM mode 186Internal Specifications Back up with hard power down mode 188189 BackINPUT/OUTPUT Ports 190Page Outline PortPort 0 internal equivalent circuit 193 Internal BUS ReadWPO Modify 194 Port 0 pin tablePort 196 Control Modify Port Read WP1Port 1 internal equivalent circuit 197 OFFInternal BUS Read OFF 198 199 On P3 On P2 Internal BUS Readoff N200 Port 1 CPU control pin tablePort 1 pin table PC/DATA DPH Port Read Modify WP2 ControlPort 2 internal equivalent circuit 202 PORT2Internal BUS Control Modify Read Data WP3204 Port 3 CPU control pin function tablePort 3 pin table INPUT/OUTPUT Ports Power Down Iocon 0F8H 206Modify Port Read Internal BUS INPUT/OUTPUT Ports CPU 1 OUT 12 NPN transistor direct connection circuit209 CPU 0 OUTPort Output Timing One machine cycle instruction output timing16 Two machine cycle instruction port output time chart Two machine cycle instruction output timingPort Data Manipulating Instructions 213 MSM80C154/83C154/85C154 214Electrical Characteristics Absolute Maximum Ratings Operational RangesPort 0, ALE, Psen DC CharacteristicsVCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85C SSV IV CC218 DC Characteristics 219Measuring circuits Repeated for specified input pinsRepeated for specified output pins Input logic for specified statusExternal Program Memory Access AC Characteristics ALE Psen Port 222External program memory read cycle InstrExternal Data Memory Access AC Characteristics Output224 External data memory read cycleExternal data memory write cycle Output Data Setup to Clock Rising Edge TQVXH 226 Machine Cycle ALE Shift Clock Output Data Input DataFloating AC Characteristics Measuring ConditionsInput/output signal Test PointExterminal Oscillator Signal XTAL1 External Clock Input Waveform ConditionsDescription of Instructions Page Description of Instructions Description of Instruction Symbols List of Instructions MSM80C154S/MSM83C154SInstruction table Simplified Description of Instructions Address in this description235 CLR a CPL a RL a RLC a RR a RRC a Swap a236 XRL MOVCLR 238MOV Dptr Setb239 Movc A, @A+PC240 Sjmp Interrupt Enable AjmpLjmp JMP @A+DPTR242 Then Else Cjne243 Then Else Djnz244 Movx A, @DPTR 245External RAM NOPDetailed Description of MSM80C154S/MSM83C154S Instructions Acall code address Absolute call within 2K bytesADD A, #data Add immediate data 247RS1 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address 248ADD A, Rr Add register 249MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory 250Addc A, #data Add carry plus immediate data to accumulator 251252 ADD A, Rr Add carry plus register to accumulator 253254 Ajmp code address Absolute jump within 2K byte 255256 ANL A, @Rr Logical and indirect address to accumulator 257258 ANL A, data address Logical and memory to accumulator 259260 ANL C,/bit address Logical and complement bit to carry flag 261262 ANL data address, a Logical and accumulator to memory 263264 Testajmp TEST1 265LOC OBJ Source Compcjne @R1, #05H, Test266 SS1MOV R7, a 267Cjne A, #0AH, SS1 LOC OBJ Source Compcjne A, #0AH, SS1268 Compcjne A, 50H, Next 269Cjne A, 50H, Next LOC OBJ Source Callcall Test270 Compared data is not equal. If the compared data is equal271 Countinc R4MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator 272CLR C Clear carry flag 273MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit 274CPL a Complement accumulator 275MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag 276CPL bit address Complement bit 277MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator 278279 280 DEC a Decrement accumulator 281MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register 282DEC data address Decrement memory 283MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by B 284AC F0 RS1 RS0 OV F1 285 Loopadd A, R7 286Djnz R1, Loop LOC OBJ Source Countdjnz R1, Loop287 288 Djnz 57H, Loop LOC OBJ SourceCountdjnz 57H, Loop INC @Rr Increment indirect address 289MSM80C154S/83C154S/85C154HVS INC a Increment accumulator 290RS1 RS0 PSW INC Dptr Increment data pointer291 DPH DPLMSM80C154S/83C154S/85C154HVS INC Rr Increment register 292INC data address Increment memory 293294 295 Bittsjb 34.3, EnterACA0 Entermov R4, 0A0H 296 297 298 Jmpcjc Carry 299Checkacall Addr Carryinc @R1300 Byte DescriptionJNB bit address, code address Jump if bit is not set 301302 Testjnb 37.3, ExitExitmov A, @R0 JNC code address Jump if carry is not set 303304 Testjnc ExitExitmov B, ACC JNZ code address Jump if accumulator is not 305Checkjnz Test 306JNZ Test LOC OBJ Source Testmov R3, aJZ code address Jump if accumulator is not 307Emptyinc a 308JZ Empty LOC OBJ Source Checkjz EmptyLcall code address Long call 309MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump 310MOV @Rr, #data Move immediate data to indirect address 3116AH 312 6CHMOV @Rr, data address Move memory to indirect address 313314 MOV A, @Rr Move indirect address to accumulator 315316 MOV A, data address Move memory to accumulator 317318 MOV DPTR, #data Move immediate data to data pointer 319DPH·DPL 320 MOV Rr, a Move accumulator to register 321322 5AHMOV bit address, C Move carry flag to bit 323324 MOV data address, @Rr Move indirect address to memory 325326 MOV data address, Rr Move register to memory 3276BH 328 329 Movc A, @A+DPTR330 331 62CCH332 333 DPL DPH57AFH 334 MUL AB Multiply accumulator by B 335MSM80C154S/83C154S/85C154HVS NOP No operation 336ORL A, #data Logical or immediate data to accumulator 337338 ORL A, Rr Logical or register to accumulator 339340 ORL C, bit address Logical or bit to carry flag 341342 ORL data address, #data Logical or immediate data to memory 343344 POP data address Pop stack to memory 345346 RET Return from subroutine, non interrupt 347348 RL a Rotate accumulator left 349RS1 RS0 OV F1 P PSW 350 RR a Rotate accumulator right 351352 Setb C Set carry flag 353MSM80C154S/83C154S/85C154HVS Setb bit address Set bit 354Sjmp code address Short jump 355356 Sjumpsjmp CheckCheckrlc a 357 358 Subb A, Rr Substract register from accumulator with borrow 359360 Swap a Exchange nibble in accumulator 361362 XCH A, Rr Exchange register with accumulator 363364 7AH365 366 367 368 369 370 371