Sonic Alert msm83c154s Multi-processor systems 128, 129, 140, 142, 146, 169, 192, 195, 201, 203

4.6.4.2 Multi-processor systems	128
4.7 Interrupt	129
4.7.1 Outline	129
4.7.2 Interrupt enable register (IE)	131
4.7.3 Interrupt priority register (IP)	132
4.7.3.1 Priority interrupt routine flow	133
4.7.3.2 Interrupt routine flow when priority circuit is stopped	134
4.7.3.3 Interrupt priority when priority register (IP) contents are all “0”	135
4.7.4 Detection of external interrupt signals INT0 and INT1	136
4.7.4.1 Outline of INT signal detection	136
4.7.4.2 External interrupt signal 0 and 1 level detection	136
4.7.4.3 External interrupt signal 0 and 1 trigger detection	137
4.7.5 MSM80C154S/MSM83C154S interrupt response time charts	138
4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied
during execution of ordinary instruction in main routine	138

4.7.5.2Interrupt response time chart when interrupt conditions are satisfied during execution of IE or IP register operation instruction in main

routine	140
4.7.5.3 Interrupt response time chart when an ordinary instruction is
executed after temporarily returning to the main routine from
continuous interrupt processing	142

4.7.5.4Interrupt response time chart when an IE or IP manipulating instruction is executed after temporarily returning to the main

		routine from continuous interrupt processing	144
4.8 CPU “Power Down”			146
4.8.1	Outline		146
4.8.2 Idle mode (IDLE) setting			146
4.8.3 Soft power down mode (PD) setting			151
4.8.3.1 Caution about software power down mode setting			151
4.8.4 Hard power down mode (HPD) setting			161
4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 169
4.9.1	Outline		169
4.9.2 Cancellation by CPU resetting (RESET pin)			169
4.9.3 Cancellation of CPU power down mode(IDLE, PD)by interrupt signal ....			176
4.9.3.1		Cancellation of CPU power down mode (IDLE, PD) from interrupt
		address	176
4.9.3.2		Cancellation of CPU power down mode (IDLE, PD) by interrupt
		request signal and restart from next address of stop address	182
4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode			187

5. INPUT/OUTPUT PORTS

5.1	Outline	192
5.2	Port 0	192
5.3	Port 1	195
5.4	Port 2	201
5.5	Port 3	203
5.6	Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down
	Mode (PD, HPD)	205