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Sonic Alert msm85c154hvs, msm83c154s, msm80154s Lnternal Data Memory RAM Operating Procedures

Models: msm83c154s msm85c154hvs msm80154s

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INTERNAL SPECIFICATIONS

4.3 lnternal Data Memory (RAM) Operating Procedures

4.3.1 Internal data memory indirect addressing

Operation of the internal data memory indirect increment instruction is described here as an example. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 4- 4). The indirect address register is specified by instruction code bit 0 data r where r denotes either register 0 or 1 in the register group specified by PSW RS0 and RS1 bank data. Register 0 is specified when the r data is 0, and register 1 is specified when the data is 1.

When this instruction is executed, register data is read from the specified register 0 or 1, and the read out register data is written into the data pointer for the data memory.

The data memory contents specified by the data pointer are read by the CPU into a temporary register. Then a subsequent increment (+1) by the ALU is followed by a return to the data memory at the address where the data were read out. In this way, the contents of the data memory at the address specified by the contents of R0 or R1 are incremented.

INC @Rr:

Instruction (OP)			Register
code portion			designation portion
				Byte 1
0 0 0 0 0 1			1 r	Byte 1

7 6 5 4 3 2 1 0

Figure 4-4 INC @Rr bit arrangement

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Sonic Alert msm85c154hvs Lnternal Data Memory RAM Operating Procedures, Internal data memory indirect addressing

Contents

MSM80C154S MSM83C154S Page Contents Reset Schmitt trigger circuit CPU internal status by reset 2.5.22.5.3 2.5.4Power down mode 3.4.2 T2EXtimer/counter 2 external flag input detector3.1 Special function registers for serial port 101 2.1Multi-processor systems 128 129140 142KW Pull-Up Resistance Setting for Quasi-bidirectional Input 207208 210Introduction Page Introduction MSM80C154S/MSM83C154S/MSM85C154HVS OutlineMSM80C154S/83C154S/85C154HVS MSM80C154S/MSM83C154S Features MSM80C154S/83C154S/85C154HVS Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS MSM80C154S/83C154S/85C154HVS System Configuration Page MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols MSM80C154S/MSM83C154S pin layouts MSM80C154SRS/MSM83C154SRSMSM80C154S/MSM83C154S pin layout top view Applicable Packages 1 MSM80C154S/MSM83C154S external dimensions MSM80C154S/MSM83C154S external dimensionsMSM80C154STS/MSM83C154STS 2 MSM85C154HVS pin layout and external dimensions MSM85C154HVS pin layout and external dimensionsSignal TIMER/COUNTER 0&1 Interrupt Serial IOSpecial Function Register AddressROM Special DPL PLA Register AddressSense AMP TH1 TL1 TH0 TL0 Tmod TconSignal DPH T2CON TL2 TH2 AMP ACC TR2 TR1Address Decoder TH1 TL1 TH0 TL0Timing and Control Outline of MSM80C154S/MSM83C154S timingTiming 9MSM80C154S/MSM83C154SMajor synchronizing signals XTAL1 ALE Psen Inst PORT-0 PCL OUT PORT-2 PCH OUT External program memory read cycle timing chartMovx A, @Rr 12 MSM80C154S Movx @Rr, a execution 13 MSM80C154S Movx A, @DPTR executionPIN Data CPU Data PIN Data Stable Sampled MOV direct, Port 0, 1, 2, 3 executionXTAL1 ALE Psen 4 MSM83C154S fundamental operation time charts 16 MSM83C154S Movx A, @Rr execution18 MSM83C154S Movx A, @DPTR execution 19 MSM83C154S Movx @DPTR, a executionPIN Data PIN Data Stable CPU Data Sampled 20 MSM83C154S MOV direct, PORT0, 1, 2, 3 executionInstruction Register IR and Instruction Decoder PLA AIRPLA Wair PLA WIRArithmetic Operation Section PSW0D0H CY AC F0 RS1 RS0 OV F1 PProgram Counter CPU Internal Data BUSProgram Memory and External Data Memory 24 MSM80C154S/MSM83C154S program areaALE Latch System Configuration Dptr XTAL1 ALE Psen Page MSM80C154S/MSM83C154S By register R0 or R1Data Control Page Crystal resonator connection diagram Oscillators XTAL1 XTAL2Supply of 50% duty clock Clock XTAL2Outline CPU ResettingCPU Reset Control ROM mode 5ResetexecutionChart Chart XTAL1 Psen ALE MSM80C154S/83C154S/85C154HVS Reset Schmitt trigger circuit Reset Schmitt trigger gate detector time chartMSM80C154S/MSM83C154S reset internal status CPU internal status by resetDenotes direct resetting even if XTAL1·2 has stopped EA CPU Memory Separate Internal Specifications Page Internal Specifications Internal Data Memory RAM and Special Function RegistersData memory and special function register layout Internal Data Memory RAM Internal data memory RAMRAM layout diagram Internal data memory registers R0 thru R7 Program status word PSWRS0 User Data RAMMSM80C154S/83C154S/85C154HVS Stack Stack storage layoutPC5 PC1Lnternal Data Memory RAM Operating Procedures Internal data memory indirect addressingDEC Rr bit arrangement Register designation table Internal data memory 1-bit data designation CLR bit address bit arrangementBit designation table Addressing combination table2AH 2BH 2EHSpecial Function Registers TCON, SCON,.... ACC, B List of special function registers Special function registers 4.4.2.1 Timer mode register Tmod MSM80C154S/83C154S/85C154HVS Power control register Pcon Timer control register Tcon SCON.6 SM1 SM0 Mode MSB LSB SconSM0 SM1 SM2 REN TB8 RB8 SCON.0Interrupt enable register IE MSB LSBET2 ET1 EX1 ET0 EX0 ET2PCT MSM80C154S/83C154S/85C154HVS Interrupt priority register IPPCT PT2 PT1 PX1 PT0 PX0 Program status word register PSW MSM80C154S/83C154S/85C154HVS 2.8 I/O control register Iocon Timer 2 control register T2CON TF2 EXF2EXEN2 TF2Timer/Counters 0, 1 and 2 4.5.1 Outline Timer/counters 0 and 1 4.5.2.1 OutlineTimer/counter 0 and 1 counting control Timer control register Tcon 88HCircuit for timer/counters 0 Overall clock input controlTimer mode register Tmod 89H PD & HPD External clock detector circuit for timer/counters 0Timer Counting control of timer/counters 0 and 1 by INT pin Detector circuit operational time chartDetector Timer ClockTimer Gate TR0 INT0 RUN Stop TR1 INT1 Mode 11 Timer mode register Tmod 89HTimer Counter T0 PIN Detector Port TR0 Gate INT0 PIN Data Detector TF0 TL0 TH0 5BITS 8BITST1 PIN Detector Port TR1 Gate INT1 PIN Data Latch Detector TF1 TL1 TH1 5BITS 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode Detector TF0 TH0 8BITSLatch Detector TF1 TH1 8BITS O ClockMSM80C154S/83C154S/85C154HVS Mode T0 PIN Detector Port TF0 8BITS TR0 GateINT0 PIN 8BITS Data Reload Data XtalDetector TF0 T0 PIN Detector Port TR0 Gate INT0 PIN Data Latch XtalTL0 8BITS Detector TF1 TH0 C 8BITS2.5.6 32-bit timer mode T0 PIN DetectorIocon 0F8H Serr IZCTimer Reset 19 T0, T1 external clock detector circuitInternal Specifications Bit is 0, and valid when Mode 1 or 3 has been set12 Timer 2 control register T2CON 0C8H Must be reset to 0 by software Timer/counter 2 operation modes3.3.1 16-bit auto reload mode To 0 by software3.3.2 16-bit capture mode TR2 Detector EXEN2 RCAP2L RCAP2H TF2 Timer EXF2 InterruptRCLK=0 TCLK=0 TL2 TH2 BIT3.3.3 16-bit baud rate generator mode 21 Timer/counter 2 16-bit capture mode circuitBaud Reset Timer Counter T2EX 3.4.2 T2EX timer/counter 2 external flag input detectorReset Timer Counter Clock Timer/counter detector circuit Detector PD & HPD O ClockSerial Port Sbuf R 100RX Control Input Shift Register Internal Specifications 102 15 SconSbuf serial port buffer register TclkRclk 16 Serial port operation modesMSM80C154S/83C154S/85C154HVS Smod Serr Mode 0 receive operation Mode 0 baud rateMode 0 transmit operation Port mode 107108 Serial port modeTiming chart 109 MSM80C154S/83C154S/85C154HVS Mode Outline Mode 1 baud rateMode 1 transmit operation Mode 1 receive operationMSM80C154S/83C154S/85C154HVS Mode 1 Uart error detection Start Serr RXD Internal BUS TIMER/COUNTER1 SMOD=1 Overflow SMOD=0113 114 Mode Outline Mode 2 baud rateMode 2 transmit operation Mode 2 receive operationMode 2 Uart error detection Internal BUS Write Start TBB Sbuf TXD To Sbuf Baud Rate SMOD=1 Clock XTAL1·2 Couter SMOD=0 Serial Port118 Mode 3 baud rate Mode 3 transmit operation Mode 3 receive operationMode 3 Uart error detection 122 123 QHSHIFT/ Load Serial Clock Inhibit F E D C B a InputRXD PX.X TXD RX.X TXDQhqg QF QE Qdqc QB QA CLKRXD TXD PX.X PX.X RXD TXD126 SHIFT/ Load Serial ClockOutput PX.X Control RXD Input PX.X Control TXD42 lnput/output extension example timing chart 127Master Slave MSM80C154S/83C154S/85C154HVS Multi-processor systemsTXD RXD Interrupt 18 lnterrupt addressesEquivalent circuit 130Interrupt control 19 lnterrupt enable register IE, 0A8H ET1PX1 20 nterrupt priority register IP, 0B8HPriority interrupt routine flow Clrea 21 Non-priority interrupt order of preference External interrupt signal 0 and 1 level detection 22 TCON88H registerTF1 TR1 TF0 IE1 IT1 IE0 IT0External interrupt signal 0 and 1 trigger detection BUS Tcon ResetPage 139 Page 141 Page 143 Page 145 CPU Power Down Idle mode Idle settingXtal Control PCON, 87H Smod HPD RPD GF1 GF0 IDL Xtal TIMER, S-I/O Interrupt147 23 CPU pin details in idle mode 148Idle 14955Idlemodesettingtime 150Soft power down mode PD setting Mode equivalent circuit 152CPU Clock Pcon 87H Control Smod HPD RPD GF1Pdreset Reset ENDPCON5RPD Pdreset 153TIMER0 15424 CPU pin details ALF=0 in soft power down mode PD 155156 Soft power down mode settingTime chart internal ROM mode Soft 25 CPU pin details ALF=1 in soft power down mode PD 158Down 15963Softpowerdownmodesetting 160Hard power down mode HPD setting Xtal Hpdi Control Pcon 87H Smod HPD RPD GF1 GF0 IDL Hard power down162 26 CPU pin details ALF=0 in hard power down mode HPD 163164 Mode165 27 CPU pin details ALF=1 in hard power down mode HPD 166167 68Hardpowerdownmodesetting 168Cancellation by CPU resetting Reset pin MSM80C154S/83C154S/85C154HVS By reset internal ROM mode170 171 172 By reset external ROM mode 173Mode by reset internal ROM mode 174Mode by reset external ROM mode 17529 Power control register Pcon 87H Smod HPD RPD GF1 GF0 IDLIDLE, PD Mode Interrupt Restart 177INT 179 Internal ROM mode 180181 IDLE, PD Mode Restart Mode SET Smod HPD RPD GF1 GF0 OUT Level Sense 184 Restart from idle mode byOr 1 external ROM mode Or 1 internal ROM mode 185External ROM mode 186Internal Specifications Back up with hard power down mode 188189 BackINPUT/OUTPUT Ports 190Page Port 0 internal equivalent circuit OutlinePort WPO Modify 193Internal BUS Read 194 Port 0 pin tablePort Port 1 internal equivalent circuit 196Control Modify Port Read WP1 Internal BUS Read OFF 197OFF 198 199 On P3 On P2 Internal BUS Readoff NPort 1 pin table 200Port 1 CPU control pin table Port 2 internal equivalent circuit PC/DATADPH Port Read Modify WP2 Control 202 PORT2Internal BUS Control Modify Read Data WP3Port 3 pin table 204Port 3 CPU control pin function table INPUT/OUTPUT Ports Modify Port Read Internal BUS Power Down Iocon 0F8H206 INPUT/OUTPUT Ports CPU 1 OUT 12 NPN transistor direct connection circuit209 CPU 0 OUTPort Output Timing One machine cycle instruction output timing16 Two machine cycle instruction port output time chart Two machine cycle instruction output timingPort Data Manipulating Instructions 213 MSM80C154/83C154/85C154 214Electrical Characteristics Absolute Maximum Ratings Operational RangesDC Characteristics VCC=4.0 to 6.0V,VSS=0V, Ta=-40C to +85CPort 0, ALE, Psen SSV IV CC218 DC Characteristics 219Repeated for specified input pins Repeated for specified output pinsMeasuring circuits Input logic for specified statusExternal Program Memory Access AC Characteristics 222 External program memory read cycleALE Psen Port InstrExternal Data Memory Access AC Characteristics OutputExternal data memory write cycle 224External data memory read cycle Output Data Setup to Clock Rising Edge TQVXH 226 Machine Cycle ALE Shift Clock Output Data Input DataAC Characteristics Measuring Conditions Input/output signalFloating Test PointExterminal Oscillator Signal XTAL1 External Clock Input Waveform ConditionsDescription of Instructions Page Description of Instructions Description of Instruction Symbols Instruction table List of InstructionsMSM80C154S/MSM83C154S Simplified Description of Instructions Address in this description235 CLR a CPL a RL a RLC a RR a RRC a Swap a236 XRL MOV238 MOV DptrCLR Setb239 Movc A, @A+PC240 Interrupt Enable Ajmp LjmpSjmp JMP @A+DPTR242 Then Else Cjne243 Then Else Djnz244 245 External RAMMovx A, @DPTR NOPDetailed Description of MSM80C154S/MSM83C154S Instructions Acall code address Absolute call within 2K bytesRS1 ADD A, #data Add immediate data247 MSM80C154S/83C154S/85C154HVS ADD A, @Rr Add indirect address 248ADD A, Rr Add register 249MSM80C154S/83C154S/85C154HVS ADD A, data address Add memory 250Addc A, #data Add carry plus immediate data to accumulator 251252 ADD A, Rr Add carry plus register to accumulator 253254 Ajmp code address Absolute jump within 2K byte 255256 ANL A, @Rr Logical and indirect address to accumulator 257258 ANL A, data address Logical and memory to accumulator 259260 ANL C,/bit address Logical and complement bit to carry flag 261262 ANL data address, a Logical and accumulator to memory 263264 265 LOC OBJ SourceTestajmp TEST1 Compcjne @R1, #05H, Test266 267 Cjne A, #0AH, SS1 LOC OBJ SourceSS1MOV R7, a Compcjne A, #0AH, SS1268 269 Cjne A, 50H, Next LOC OBJ SourceCompcjne A, 50H, Next Callcall Test270 Compared data is not equal. If the compared data is equal271 Countinc R4MSM80C154S/83C154S/85C154HVS CLR a Clear accumulator 272CLR C Clear carry flag 273MSM80C154S/83C154S/85C154HVS CLR bit address Clear bit 274CPL a Complement accumulator 275MSM80C154S/83C154S/85C154HVS CPL C Complement carry flag 276CPL bit address Complement bit 277MSM80C154S/83C154S/85C154HVS DA a Decimal adjust accumulator 278279 280 DEC a Decrement accumulator 281MSM80C154S/83C154S/85C154HVS DEC Rr Decrement register 282DEC data address Decrement memory 283AC F0 RS1 RS0 OV F1 MSM80C154S/83C154S/85C154HVS DIV AB Divide accumulator by B284 285 286 Djnz R1, Loop LOC OBJ SourceLoopadd A, R7 Countdjnz R1, Loop287 Countdjnz 57H, Loop 288Djnz 57H, Loop LOC OBJ Source INC @Rr Increment indirect address 289MSM80C154S/83C154S/85C154HVS INC a Increment accumulator 290INC Dptr Increment data pointer 291RS1 RS0 PSW DPH DPLMSM80C154S/83C154S/85C154HVS INC Rr Increment register 292INC data address Increment memory 293294 ACA0 Entermov R4, 0A0H 295Bittsjb 34.3, Enter 296 297 298 299 Checkacall AddrJmpcjc Carry Carryinc @R1300 Byte DescriptionJNB bit address, code address Jump if bit is not set 301Exitmov A, @R0 302Testjnb 37.3, Exit JNC code address Jump if carry is not set 303Exitmov B, ACC 304Testjnc Exit JNZ code address Jump if accumulator is not 305306 JNZ Test LOC OBJ SourceCheckjnz Test Testmov R3, aJZ code address Jump if accumulator is not 307308 JZ Empty LOC OBJ SourceEmptyinc a Checkjz EmptyLcall code address Long call 309MSM80C154S/83C154S/85C154HVS Ljmp code address Long jump 3106AH MOV @Rr, #data Move immediate data to indirect address311 312 6CHMOV @Rr, data address Move memory to indirect address 313314 MOV A, @Rr Move indirect address to accumulator 315316 MOV A, data address Move memory to accumulator 317318 DPH·DPL MOV DPTR, #data Move immediate data to data pointer319 320 MOV Rr, a Move accumulator to register 321322 5AHMOV bit address, C Move carry flag to bit 323324 MOV data address, @Rr Move indirect address to memory 325326 6BH MOV data address, Rr Move register to memory327 328 329 Movc A, @A+DPTR330 331 62CCH332 57AFH 333DPL DPH 334 MUL AB Multiply accumulator by B 335MSM80C154S/83C154S/85C154HVS NOP No operation 336ORL A, #data Logical or immediate data to accumulator 337338 ORL A, Rr Logical or register to accumulator 339340 ORL C, bit address Logical or bit to carry flag 341342 ORL data address, #data Logical or immediate data to memory 343344 POP data address Pop stack to memory 345346 RET Return from subroutine, non interrupt 347348 RS1 RS0 OV F1 P PSW RL a Rotate accumulator left349 350 RR a Rotate accumulator right 351352 Setb C Set carry flag 353MSM80C154S/83C154S/85C154HVS Setb bit address Set bit 354Sjmp code address Short jump 355Checkrlc a 356Sjumpsjmp Check 357 358 Subb A, Rr Substract register from accumulator with borrow 359360 Swap a Exchange nibble in accumulator 361362 XCH A, Rr Exchange register with accumulator 363364 7AH365 366 367 368 369 370 371