102
STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.5.15 ETX TxFIFO Read Pointer
This nine-bit loadable counter points to the next location in the FIFO that will
be read from to retrieve packet data that is transferred to the TX_MAC. The
counter increments by 1 or 2 (depending on SBus configuration) after a word
(or double word) was read from the FIFO. The counter is loaded with the con-
tents of the shadow read pointer, when a retry occurs due to a collision on the
network. This counter is used to generate the read address for the TxFIFO
memory core.
7.5.16 ETX TxFIFO Shadow Read Pointer
This nine-bit register points to the first byte of the packet that is either cur-
rently being unloaded or is about to be unloaded from the TxFIFO. The reg-
ister is loaded with the contents of the read pointer after the packet transfer
from the FIFO to the TX_MAC has been completed. This register is used to
Table 114: ETX TxFIFO Shadow Write Pointer Register Address
Register Physical Address Access Size
TxFIFO shadow write pointer register 0x8C0_2018 4 bytes
Table 115: ETX TxFIFO Shadow Write Pointer Register Definition
Field Bits Description Type
TxFIFO shadow write pointer 8:0 Points to the first byte of the packet
that is either currently being loaded or
is about to be loaded into the FIFO.
R/W
Table 116: ETX TxFIFO Read Pointer Register Address
Register Physical Address Access Size
TxFIFO read pointer register 0x8C0_201C 4 bytes
Table 117: ETX TxFIFO Read Pointer Register Definition
Field Bits Description Type
TxFIFO read pointer 8:0 Counter that points to next location in
FIFO that will be read from to retrieve data
that will be transferred to TX_MAC
R/W