Sun Microsystems STP2002QFP 7.5.9 ETX Transmit Data Buffer Base Address, 7.5.10 ETX Transmit Data Buffer Displacement (RO)

99
STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
Default: 0xF; 256 descriptor entries.
7.5.9 ETX Transmit Data Buffer Base Address
7.5.10 ETX Transmit Data Buffer Displacement (RO)
This 10-bit counter keeps track of the next DVMA read burst address. It is
used as a displacement for the data buffer base address. The counter incre-
ments by 1, 2, or 4 (depending on the burst size) after a DVMA read burst cy-
cle has been executed by the transmit DMA engine. The counter is cleared
when the data buffer base address is loaded by the DMA state machine. This
register is used to generate the DVMA burst address by adding it to the buffer
base address.
Table 103: ETX Transmit Descriptor Ring Size Register Address
Register Physical Address Access Size
ETX transmit descriptor ring size register 0x8C0_202C 4 bytes
Table 104: ETX Transmit Data Buffer Base Address Register Address
Register Physical Address Access Size
ETX transmit data buffer base address register 0x8C0_200C 4 bytes
Table 105: ETX Transmit Data Buffer Base Address Register Definition
Field Bits Description Type
Transmit data
buffer base address
31:0 This 32-bit register points to the beginning of
the transmit data buffer in the host memory. It
is loaded by the DMA state machine during the
descriptor fetch phase. This register is used to
generate the DVMA burst address by adding to
it the data buffer displacement.
R
Table 106: ETX Transmit Data Buffer Displacement Register Address
Register Physical Address Access Size
ETX transmit data buffer displacement register 0x8C0_2010 4 bytes