65
STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
Note:The P_TST_CSR is intended for diagnostic and test use only and should never be
written while a DMA transfer is active
7.2.5 Hardware Configuration Register

Table 26: Test Control/Status Register Definition

Field Bits Description Type
LD_TAG 31 When set to 1. loads FIFO DMA address register
(ADDR_TAG) with value in D_ADDR
W
REQ_OUT 30 Reads as 1, when FIFO is making a request for an
SBus read or write.
R
RD_BURST 30 When set to 1, initiates a DMA burst read from
memory into FIFO from address in ADDR_TAG
W
WR_CNT 29 When set to 1, loads FIFO_CNT register with
D_TST_CSR[5:0]
W
WRITE 28 When set to 1, puts FIFO into WRITING mode.
Reads as 1 when FIFO in WRITING mode.
R/W
DRAIN 27 Reads as 1 if FIFO is draining. When set to 1,
forces FIFO to drain.
R/W
EMPTY 26 Reads as 1, if FIFO buffer empty. R
FULL 25 Reads as 1, if FIFO buffer is full. R
LO_MARK 24 Reads as 1, if FIFO buffer has enough room for 1
SBus read burst of data.
R
HI_MARK 23 Reads as 1, if FIFO contains enough data for 1
SBus write burst.
R
COUNT 5:0 Reads CNT register containing number of bytes
stored in FIFO buffer.
R
COUNT 5:0 When WR_CNT=1, write CNT register contain-
ing number of bytes stored in FIFO buffer.
W

Table 27: Hardware Configuration Register Address

Register Physical Address Access Size
Hardware configuration register (P_HCR) 0xC80_0010 2 bytes