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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
The above signals describe the I/O signals of the JTAG macro. The JTAG
macro is composed of the following blocks: TAP controller, instruction reg-
ister, instruction decode logic, bypass register, internal register clocking
logic, JTAG ID register, JTAG boundary scan control logic, and the TDO
MUX logic.
The following sections describe each of these blocks.
6.2.1 TAP ControllerThe TAP controller is a 16-state finite state machine. Transitions between
states occur synchronously at the rising edge of JTAG_TCK in response to
the JTAG_TMS signal or whenJTAG_TRST goes low.
Table 16: JTAG Macro I/O Signals
JTAG_TCK JTAG clock from chip pads
JTAG_TDI JTAG test data in from chip pads
JTAG_TDO JTAG test data out to chip pads
JTAG_TRST JTAG test reset from chip pads
JTAG_TMS JTAG mode select from chip pads
JTAG_TDO_EN JTAG test data out enable to chip pads
BSCAN_CDR Boundary scan clock data register
BSCAN_SDI Boundary scan data input (to BSCAN cells)
BSCAN SDR Boundary scan shift data register
BSCAN_UDR Boundary scan update data register
BSCAN_IMC Boundary scan input mode control
BSCAN_OMC Boundary scan output mode control
BSCAN_TDO Boundary scan test data output
ISCAN_CLK Internal scan clock
ISCAN_SDR Internal shift select
ISCAN_SDI Internal scan data input
ISCAN_TDO Internal scan test data output
SCSI_SELECT SCSI test mode select signal
ISCAN_MODE Internal scan mode select signal