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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.2.7 Parallel Data Register
Thedata register is an 8-bit read/write port used to transfer data to and from
the external device. In programmed I/O mode data written to this register is
presented to the I/O pins if theDIR bit of thetransfer control register is 0. A
read of this register will result in the data previously written or if theDIR bit
of the transfer control register is set to 1, the latched data from the last data
strobe. The data port isnot accessible via slave write cycles during DMA
(P_DMA_ON=1). Any write cycles during DMA will not generate errors, the
data will simply not be written.
Since both DMA and PIO share the same data register, internal loopback
is possible by running a single-byte DMA cycle followed by a PIO cycle to
verify the data. This will test both the DMA and slave data paths.
7.2.8 Transfer Control Register
Thetransfer control register is an 8-bit register whose contents define/reflect
the state of the external interface handshake and direction control signals. The
DS, ACK, and BUSYbits will reflect the state of the external pins, when read.
Writing these bits defines a value to be driven onto the external pins if the in-
dividual direction select bits (DS_DSEL, ACK_DSEL, BUSY_DSEL) and
the direction control bit (DIR) are configured such that the HIOD is driving
these pins as outputs. The write bits and read bits are different. That means
that values typically written to these bits may not be reflected on a read cycle.
However, by setting the EN_DIAG bit of the operation control register, these
register bits become read/write (see the EN_DIAG bit description of the
OCR).
Table 31: Parallel Data Register Address
Register Physical Address Access Size
Parallel data register (P_DR) 0xC80_0014 1 byte
Table 32: Parallel Data Register Definition
Field Bits Description Type
P_DR 7:0 Parallel data R/W