54
STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
6.2.5 Internal Register Clocking Logic
This module generates the scan clock for the internal scan flops and the scan
enable to for the scan flops.
Figure 20.
6.2.6 JTAG ID Register
This is a 32-bit shift register which has four fields. The least significant bit is
a 1, the next 11 bits [11:1] are the manufacturer’s ID, the next 16 bits [27:12]
are the chip ID, and the most significant 4 bits [31:28] are the chip vintage.
The JTAG ID for FEPS Rev 1.0 is 01792045 hex, for FEPS Rev 2.0 and 2.1
it is 11792045 hex, and for FEPS Rev 2.2 it is 21792045 hex.
Figure 21.
6.2.7 Boundary Scan Control Logic
This block generates the boundary scan clock and the boundary scan shift and
update signals which form part of the boundary scan control bus that runs
along the boundary scan chain. This control bus feeds the boundary scan
cells.
ISCAN_MODE
DEBUG_SELEC
T
DR_CLOCK
DR_CAPTURE
DR_SHIFT
ISCAN_DR
ISCAN_CLK
IS_CLOCK
JTAG_TDI
DR_CLOCK
DR_SHIFT
ID_SELECT
ID_TDO
JTAG_ID