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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
The size of the descriptor ring is programmable, and it can be varied in the
range of 16–256 in increments of 16 descriptors: 16, 32, 48, ..., 240, 256.
5.2.6 Receive Free Buffer Descriptor Ring
For receive operation, the device driver requests a pool of free buffers from
the operating system. The buffers are posted to the hardware by allocating a
descriptor for each buffer. The descriptor contains the necessary information
about the buffer that the hardware needs for the packet transfer.
When a packet is ready to be transferred from the RxFIFO to the host mem-
ory, the receive DMA channel polls the next descriptor in the ring. If the
hardware owns the descriptor (free buffer available), the packet transfer
begins. During the first burst, the receive DMA engine performs header pad-
ding of the packet by inserting a programmable number of junk words at the
beginning of the packet.
When the packet transfer has been completed, the receive DMA channel
updates the descriptor with status information about the received packet, and
turns over the descriptor ownership back to the driver. If a packet is ready to
be transferred from the RxFIFO to the host memory but the driver does not
have any free buffers allocated to the hardware, the packet will be dropped
into the bit bucket, and the DMA channel will try again when the next packet
is ready to go.
The size of the descriptor ring is programmable and can assume the follow-
ing values: 32, 64, 128, 256.
5.2.7 Local Memory Data Management
Each DMA channel contains its own dedicated on-chip local buffer of 2K
bytes (fixed) in size. The local buffers are used for temporary storage of pack-
ets en route to/from the network, and are organized as wrap-around FIFOs.
In general, the local buffer organization and data structures are invisible to
the software, except for diagnostic purposes.
Since the local buffers reside in the data path, their logical organization
changes depending on the SBus width. For a 32-bit SBus, the FIFO organiza-
tion is 512 words× 33 bits. For a 64-bit SBus, the FIFOs are organized as 256
words× 65 bits. The extra bits (bit 33 or bit 65) along the word are used as
end-of-packet delimiters (or tags). When a packet is stored in the local buffer,
the tag will be cleared to 0 for the entire data portion of the packet, except for
the last word. The tag will be set to 1 for the last data word of the packet and
for the control/status word.