Sun Microsystems STP2002QFP 5.2.3 Clock Domains

32

STP2002QFP

Sun Microelectronics

Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP

ation can only be used when the MIF is in the frame mode.

5.2.2.3 Ethernet Transmit Block (ETX)

The Ethernet transmit block provides the DMA engine for transferring frames

from the host memory to the BigMAC. It contains a local buffer of 2K bytes

for rate adaptation between the available bandwidth on the SBus and on the

network.

5.2.2.4 Ethernet Receive Block (ERX)

The Ethernet receive block provides the DMA engine for transferring frames

from the BigMAC to the host memory. It contains a local buffer of 2K bytes

for rate adaptation between the available bandwidth on the network and on

the SBus.

5.2.2.5 Shared Ethernet Block (SEB)

The shared Ethernet block contains common functions that are shared be-

tween the ETX and ERX blocks. It performs the first level arbitration be-

tween the receive and transmit DMA channels for access to the SBus and

provides one common interface between the Ethernet channel and the SBus

adapter (SBA). It also separates the DMA data path from the programmed I/O

data path.

5.2.3 Clock Domains

The Ethernet channel contains three completely asynchronous clock do-

mains.

System Clock Domain

The bulk of the logic in the Ethernet channel is driven off this clock. It is

sourced by the system bus and is defined to be in the range of 16.67 MHz

through 33.33 MHz.

Transmit Clock Domain

This clock is used to drive the transmit protocol engine in the BigMAC core.

It is sourced by the MII and has the operating frequency of 2.5/25 MHz 100

ppm. The 2.5/25 MHz version of this clock (TX_NCLK) is used for byte-to-

nibble conversion of the data stream to the MII and for synchronization of the

asynchronous signals from the MII (CRS and COLL). The 1.25/12.5 MHz di-

vide-by-two version of this clock (TX_BCLK) is used for transmit protocol

processing and state machine operation.

Contents

Main STP2002QFP STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) USERS GUIDE OVERVIEW 1 1.1 Introduction 1.4 Technology Information 1.5 Compliance Page Page 1.6 Pin Descriptions The signal pins are grouped by function in the following tables. Table 1: SBus Signals Table 2: SCSI Signals Table 3: Ethernet Signals Table 2: SCSI Signals Table 4: Parallel Port Signals Table 5: JTAG/Miscellaneous Signals Page SBUS ADAPTER 2 2.1 Introduction 2.2 SBus Capabilities 2.2.1 Slave Accesses 2.2.2 Master Accesses 2.3 Theory of Operation 2.3.1 Master Operations 2.3.2 Slave Operation SCSI CHANNEL 3 3.1 Introduction 3.2 SCSI DVMA 3.3 FAS366 3.4 Test Support PARALLEL PORT CHANNEL 4 4.1 Introduction 4.2 Parallel Port FIFO Operation 4.3 Bidirectional Parallel Port Interface 4.3.1 DMA Mode Page Page Page Page STP2002QFP Page Page Page Page 4.3.2 Programmed I/O Mode Page 4.4 Differences from STP2000 (MACIO) Parallel Port 4.5 Test Support ETHERNET CHANNEL 5 5.1 Introduction 5.2 Functional Description 5.2.1 Overview 5.2.2 Functional Blocks Page Page 5.2.3 Clock Domains 5.2.4 Host Memory Data Management 5.2.5 Transmit Data Descriptor Ring 5.2.6 Receive Free Buffer Descriptor Ring 5.2.7 Local Memory Data Management 5.2.8 Transmit FIFO Data Structures 5.2.9 Receive FIFO Data Structures 5.3 Error Conditions and Recovery 5.3.1 Fatal Errors 5.3.2 Non-Fatal Errors Page 5.4 Programmers Reference 5.4.1 Overview 5.4.2 Host Memory Data Structures 5.4.3 Transmit Data Structures nearest burst boundary and execute a full DVMA burst read. Figure 10. Transmit Host Data Structures 5.4.4 Receive Data Structures Programming Restrictions: Free receive data buffers must be 64-byte aligned. Table 12: Receive Data Structures Descriptor Layout: Status Word Table 13: Receive Data Structures: Descriptor Layout: Free Buffer Pointer 5.4.5 Local Memory Data Structures 5.4.6 TxFIFO Data Structures 5.4.7 RxFIFO Data Structures Figure 12. TxFIFO Organization 5.4.8 Other User Accessible Resources less specified otherwise. Figure 13. RxFIFO Organization T 6.1 Introduction 6.2 JTAG Macro 6.2.1 TAP Controller 6.2.2 Instruction Register Page 6.2.3 Instruction Decode Logic 6.2.4 Bypass Register 6.2.5 Internal Register Clocking Logic 6.2.6 JTAG ID Register 6.2.7 Boundary Scan Control Logic 6.2.8 TDO MUX logic 6.3 Special JTAG Instructions 6.3.1 Debug Modes 6.3.2 INTEST 6.3.3 SCSI Test Mode 6.4 Clock Stop Pin 6.5 Test Vectors PROGRAMMING MODEL 7 7.1 Introduction 7.2 Parallel Port Channel Registers 7.2.1 Control/Status Register Table 18: Control/Status Register Address Page Page Page 7.2.2 DMA Address and Next Address Register 7.2.3 Byte Count Register Page 7.2.5 Hardware Conguration Register Table 26: Test Control/Status Register Denition Table 27: Hardware Conguration Register Address 7.2.6 Operation Conguration Register Page Page Page 7.2.7 Parallel Data Register 7.2.8 Transfer Control Register Page Page 7.2.9 Output Register 7.2.10 Input Register 7.2.11 Interrupt Control Register Page 7.3 SCSI Channel Registers 7.3.1 SCSI Control/Status Register D_INT_PEND: Table 43: BURST_SIZE Encoding Table 42: Control/Status Register Denition 7.3.2 SCSI Address Register 7.3.3 SCSI Byte Count Register 7.3.4 SCSI Test Control/Status Register Page Page 7.4 FAS366 (SCSI Controller Core) Registers 7.4.1 FAS366 Transfer Counter Low Register (Read Only) 7.4.2 FAS366 Transfer Count Low Register (Write Only) 7.4.3 FAS366 Transfer Counter High Register (Read Only) 7.4.4 FAS366 Transfer Count High (Write Only) Register 7.4.5 FAS366 FIFO Register 7.4.6 FAS366 Command Register Page 7.4.8 FAS366 Select/Reselect Bus ID Register 7.4.9 FAS366 Interrupt Register 7.4.10 FAS366 Select/Reselect Time-Out Register 7.4.11 FAS366 Sequence Step Register 7.4.12 FAS366 Synchronous Transfer Period Register 7.4.13 FAS366 FIFO Flags Register 7.4.14 FAS366 Synchronous Offset Register 7.4.15 FAS366 Conguration #1 Register 7.4.16 FAS366 Clock Conversion Factor Register 7.4.17 FAS366 Status #2 Register 7.4.18 FAS366 Test Register 7.4.19 FAS366 Conguration #2 Register 7.4.20 FAS366 Conguration #3 Register 7.4.21 FAS366 Recommand Counter Register 7.5 Ethernet Channel Registers 7.5.1 Global Software Reset Register 7.5.2 Global Conguration Register 7.5.3 Global Interrupt Mask Register (RW) 7.5.4 Global Status Register Table 98: Global Status Register Denition 7.5.5 ETX Transmit Pending Command 7.5.6 ETX Conguration Register 7.5.7 ETX Transmit Descriptor Pointer (RW) 7.5.8 ETX Transmit Descriptor Ring Size 7.5.9 ETX Transmit Data Buffer Base Address 7.5.10 ETX Transmit Data Buffer Displacement (RO) 7.5.11 ETX Transmit Data Pointer 7.5.12 ETX TxFIFO Packet Counter 7.5.13 ETX TxFIFO Write Pointer 7.5.14 ETX TxFIFO Shadow Write Pointer 7.5.15 ETX TxFIFO Read Pointer 7.5.16 ETX TxFIFO Shadow Read Pointer 7.5.17 ETX State Machine Register 7.5.18 ETX TxFIFO 7.5.19 ERX Conguration Register 7.5.20 ERX Receive Descriptor Pointer Table 124: ERX Conguration Register Denition Table 125: ERX Receive Descriptor Pointer Register Address 7.5.21 ERX Receive Data Buffer Pointer 7.5.22 ERX RxFIFO Write Pointer Page 7.5.23 ERX RxFIFO Shadow Write Pointer 7.5.24 ERX RxFIFO Read Pointer 7.5.25 ERX RxFIFO Packet Counter 7.5.26 ERX State Machine Register 7.5.27 ERX RxFIFO 7.5.28 XIF Conguration Register Table 141: XIF Conguration Register Denition 7.5.29 TX_MAC Software Reset Command 7.5.30 TX_MAC Conguration Register Table 144: TX_MAC Conguration Register Denition 7.5.31 TX_MAC InterPacketGap1 Register 7.5.32 TX_MAC InterPacketGap2 Register 7.5.33 TX_MAC AttemptLimit Register 7.5.34 TX_MAC SlotTime Register 7.5.35 TX_MAC PA Size Register 7.5.36 TX_MAC PA Pattern Register 7.5.37 TX_MAC SFD Pattern Register 7.5.38 TX_MAC JamSize Register 7.5.39 TX_MAC TxMaxFrameSize Register 7.5.40 TX_MAC TxMinFrameSize Register 7.5.41 TX_MAC PeakAttempts Register 7.5.42 TX_MAC Defer Timer 7.5.43 TX_MAC Normal Collision Counter 7.5.44 TX_MAC First Successful Collision Counter 7.5.45 TX_MAC Excessive Collision Counter 7.5.46 TX_MAC Late Collision Counter 7.5.47 TX_MAC Random Number Seed Register 7.5.48 TX_MAC State Machine Register 7.5.49 RX_MAC Software Reset Command 7.5.50 RX_MAC Conguration Register Table 183: RX_MAC Conguration Register Denition 7.5.51 RX_MAC RxMaxFrameSize Register 7.5.52 RX_MAC RxMinFrameSize Register Page 7.5.54 RX_MAC MAC Address 1 Register 7.5.55 RX_MAC MAC Address 0 Register 7.5.56 RX_MAC Receive Frame Counter 7.5.57 RX_MAC Length Error Counter 7.5.58 RX_MAC Alignment Error Counter 7.5.59 RX_MAC FCS Error Counter 7.5.60 RX_MAC State Machine Register 7.5.61 RX_MAC Rx Code Violation Counter 7.5.62 RX_MAC Hash Table 3 Register 7.5.63 RX_MAC Hash Table 2 Register 7.5.64 RX_MAC Hash Table 1 Register 7.5.65 RX_MAC Hash Table 0 Register 7.5.66 RX_MAC Address Filter 2 Register 7.5.67 RX_MAC Address Filter 1 Register 7.5.68 RX_MAC Address Filter 0 Register 7.5.69 RX_MAC Address Filter Mask Register 7.5.70 MIF Bit-Bang Clock 7.5.71 MIF Bit-Bang Data 7.5.72 MIF Bit-Bang Output Enable 7.5.73 MIF Frame/Output Register 7.5.74 MIF Conguration Register This 15-bit register controls the operation of the MIF. Table 227: MIF Conguration Register Address Table 226: MIF Frame/Output Register Denition 7.5.75 MIF Mask Register Table 228: MIF Conguration Register Denition 7.5.76 MIF Status Register 7.5.77 MIF State Machine Register PIN ASSIGNMENTS 8 8.1 Pin Assignments The Table 235 describes the pin assignments for the 240-pin PQFP FEPS package. Page Page Page Page Page Page Page ERRATA 9 9.1 Description of Errata in FEPS Rev 2.2 9.1.1 SCSI DVMA/Channel Engine (CE) Page Page 9.1.2 FAS366 Core 9.1.3 Ethernet Channel