56
STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Figure 23.
6.3 Special JTAG Instructions
In addition to the mandatory instructions, the FEPS JTAG implements some
special instructions.

6.3.1 Debug Modes

6.3.1.1 Dumping Internal State
Using the DEBUG instruction, the internal chain can be selected. This in-
struction provides nondestructive internal node visibility during lab debug.
No capture clock is issued for this instruction. While the debug instruction is
selected, both the inputs and outputs are defined by the contents of the bound-
ary scan register.
6.3.1.2 Clock Controller
The clock controller will deterministically stop FEPS internal clocks upon the
occurrence of an external event. The clock controller can only be accessed via
the CCR scan chain. This chain is selected via the SEL_CCR instruction.
The clock controller consists of a stop enable bit and three synchronizers
for the SBus, ENET-Tx, and ENET-Rx domains. When the stop bit is set, the
clock_stop signal will switch the source of the internal clock from the clock
pins to the internal controller. This clock source switching is synchronized to
the rising edge for each clock domain.

6.3.2 INTEST

INTEST can be used to apply stimulus to test the on-chip logic when the chip
sits on a board. This requires that the core be driven off the input boundary-
scan cells and the core drives the output boundary-scan cells. For this we re-
quire that the clock pads be made controllable via boundary scan. INTEST
can also be used to apply burn-in vectors if the burn-in tester is pin limited
and can’t accommodate all the FEPS pins.

6.3.3 SCSI Test Mode

The SCSI Test mode will provide access to the I/O signals of the SCSI
FAS366 core through the I/O pins. This mode isolates the SCSI core by pro-
viding controllability and observability to its I/O signals. The vectors applied
will yield 95% coverage in the SCSI core area which does not have internal
scan.