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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
6.4 Clock Stop Pin
This pin can deterministically stop the clocks in FEPS. After the instruction
register is updated with the SEL_CCR instruction, an initializing pattern is
loaded into the CCR scan data register. In the run-test/idle state, any external
event which triggers the clock stop pin will switch the clock source from the
clock pins to the ISCAN_CLK signal generated by the JTAG logic. This sig-
nal is held high in the run-test/idle controller state. The switching is synchro-
nized with the rising edge of the clocks of the respective clock domains.
The clocks that need to be stopped are those that are those that control the
flops in the full scan area which are the SBus, ENET-Tx, and ENET-Rx
clocks.
Int_Scan_Enable shifts the clock between the SBus_CLK and the
ISCAN_CLK. This clock tree feeds the scan flops in the SBA, parallel port,
and SCSI DMA where the scan flops have the same system and scan clock.
ENET_Tx_Scan_En is the clock enable for the scan flops in the Ethernet
Tx clock domain. Here the scan flops have TX_CLK as the system clock and
a SBUS_CLK as the scan clock. ENET_Rx_Scan_En is the clock enable for
the scan flops in the Ethernet Rx clock domain. Here the scan flops have
RX_CLK as the system clock and a SBUS_CLK as the scan clock.
6.5 Test Vectors
The RAMs and data buffers are tested using high-coverage functional vectors
which target memory-specific faults. The full scan area is tested by combina-
tional ATPG vectors which yield a high fault coverage.