SUPER MICRO Computer 6015B-8+ manual Post Code Description

SUPERSERVER 6015B-T+/6015B-8+ User’s Manual

POST Code	Description
18h	8254 timer initialization
1Ah	8237 DMA controller initialization
1Ch	Reset Programmable Interrupt Controller
20h	1-3-1-1 Test DRAM refresh
22h	1-3-1-3 Test 8742 Keyboard Controller
24h	Set ES segment register to 4 GB
28h	Auto size DRAM
29h	Initialize POST Memory Manager
2Ah	Clear 512 kB base RAM
2Ch	1-3-4-1 RAM failure on address line xxxx*
2Eh	1-3-4-3 RAM failure on data bits xxxx* of low byte of
	memory bus
2Fh	Enable cache before system BIOS shadow
32h	Test CPU bus-clock frequency
33h	Initialize Phoenix Dispatch Manager
36h	Warm start shut down
38h	Shadow system BIOS ROM
3Ah	Auto size cache
3Ch	Advanced confi guration of chipset registers
3Dh	Load alternate registers with CMOS values
41h	Initialize extended memory for RomPilot
42h	Initialize interrupt vectors
45h	POST device initialization
46h	2-1-2-3 Check ROM copyright notice
47h	Initialize I20 support
48h	Check video confi guration against CMOS
49h	Initialize PCI bus and devices
4Ah	Initialize all video adapters in system
4Bh	QuietBoot start (optional)
4Ch	Shadow video BIOS ROM
4Eh	Display BIOS copyright notice
4Fh	Initialize MultiBoot
50h	Display CPU type and speed
51h	Initialize EISA board
52h	Test keyboard
54h	Set key click if enabled
55h	Enable USB devices
58h	2-2-3-1 Test for unexpected interrupts
59h	Initialize POST display service
5Ah	Display prompt “Press F2 to enter SETUP”
5Bh	Disable CPU cache

B-2