Intel 80C186EA, 80L186EA, 80L188EA Clkin, Oscout, Resin, Resout, Pdtmr HWH, Nmi, Test/Busy

Page 11

 

 

 

 

 

 

 

 

 

 

 

80C186EA/80C188EA, 80L186EA/80L188EA

 

 

 

 

 

 

 

 

 

Table 3. Pin Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Pin

Input

Output

 

 

Description

 

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

P

 

 

POWER connections consist of six pins which must be shorted

 

 

 

 

 

 

 

 

 

externally to a VCC board plane.

VSS

G

 

 

GROUND connections consist of five pins which must be shorted

 

 

 

 

 

 

 

 

 

externally to a VSS board plane.

CLKIN

I

A(E)

 

CLocK INput is an input for an external clock. An external

 

 

 

 

 

 

 

 

 

oscillator operating at two times the required processor operating

 

 

 

 

 

 

 

 

 

frequency can be connected to CLKIN. For crystal operation,

 

 

 

 

 

 

 

 

 

CLKIN (along with OSCOUT) are the crystal connections to an

 

 

 

 

 

 

 

 

 

internal Pierce oscillator.

 

 

 

 

 

 

 

 

 

 

 

 

OSCOUT

O

 

H(Q)

OSCillator OUTput is only used when using a crystal to generate

 

 

 

 

 

 

 

 

R(Q)

the external clock. OSCOUT (along with CLKIN) are the crystal

 

 

 

 

 

 

 

 

P(Q)

connections to an internal Pierce oscillator. This pin is not to be

 

 

 

 

 

 

 

 

 

used as 2X clock output for non-crystal applications (i.e., this pin is

 

 

 

 

 

 

 

 

 

N.C. for non-crystal applications). OSCOUT does not float in

 

 

 

 

 

 

 

 

 

ONCE mode.

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT

O

 

H(Q)

CLocK OUTput provides a timing reference for inputs and outputs

 

 

 

 

 

 

 

 

R(Q)

of the processor, and is one-half the input clock (CLKIN)

 

 

 

 

 

 

 

 

P(Q)

frequency. CLKOUT has a 50% duty cycle and transistions every

 

 

 

 

 

 

 

 

 

falling edge of CLKIN.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESIN

I

A(L)

 

RESet IN causes the processor to immediately terminate any bus

 

 

 

 

 

 

 

 

 

cycle in progress and assume an initialized state. All pins will be

 

 

 

 

 

 

 

 

 

driven to a known state, and RESOUT will also be driven active.

 

 

 

 

 

 

 

 

 

The rising edge (low-to-high) transition synchronizes CLKOUT with

 

 

 

 

 

 

 

 

 

CLKIN before the processor begins fetching opcodes at memory

 

 

 

 

 

 

 

 

 

location 0FFFF0H.

 

 

 

 

 

 

 

 

 

 

RESOUT

O

 

H(0)

RESet OUTput that indicates the processor is currently in the

 

 

 

 

 

 

 

 

R(1)

reset state. RESOUT will remain active as long as RESIN remains

 

 

 

 

 

 

 

 

P(0)

 

active. When tied to the TEST/BUSY pin, RESOUT forces the

 

 

 

 

 

 

 

 

 

 

80C186EA into Numerics Mode.

 

 

 

 

 

 

 

 

 

 

PDTMR

I/O

A(L)

H(WH)

Power-Down TiMeR pin (normally connected to an external

 

 

 

 

 

 

 

 

R(Z)

capacitor) that determines the amount of time the processor waits

 

 

 

 

 

 

 

 

P(1)

after an exit from power down before resuming normal operation.

 

 

 

 

 

 

 

 

 

The duration of time required will depend on the startup

 

 

 

 

 

 

 

 

 

characteristics of the crystal oscillator.

 

 

 

 

 

 

 

 

 

 

NMI

I

A(E)

 

Non-Maskable Interrupt input causes a Type 2 interrupt to be

 

 

 

 

 

 

 

 

 

serviced by the CPU. NMI is latched internally.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST/BUSY

I

A(E)

 

TEST/BUSY is sampled upon reset to determine whether the

 

 

 

 

 

 

 

80C186EA is to enter Numerics Mode. In regular operation, the pin

 

(TEST)

 

 

 

 

 

 

 

 

 

 

 

 

is TEST. TEST is used during the execution of the WAIT

 

 

 

 

 

 

 

 

 

instruction to suspend CPU operation until the pin is sampled

 

 

 

 

 

 

 

 

 

active (low). In Numerics Mode, the pin is BUSY. BUSY notifies the

 

 

 

 

 

 

 

 

 

80C186EA of 80C187 Numerics Coprocessor activity.

 

 

 

 

 

AD15:0

I/O

S(L)

H(Z)

These pins provide a multiplexed Address and Data bus. During

(AD7:0)

 

 

R(Z)

the address phase of the bus cycle, address bits 0 through 15 (0

 

 

 

 

 

 

 

 

P(X)

through 7 on the 8-bit bus versions) are presented on the bus and

 

 

 

 

 

 

 

 

 

can be latched using ALE. 8- or 16-bit data information is

 

 

 

 

 

 

 

 

 

transferred during the data phase of the bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Clock Generator Introduction80C186EA Core Architecture Bus Interface UnitCrystal Connection Clock Connection Timer/Counter Unit80C186EA Peripheral Architecture Interrupt Control UnitPeripheral Control Block Registers Refresh Control Unit Power ManagementDMA Control Unit Chip-Select UnitDifferences Between the 80C186XL and the 80C186EA QFP Eiaj Package InformationPin Descriptions PlccRWH Resout ClkinOscout ResinRD/QSMD ALE/QS0BHE RfshDEN WR/QS1Ardy SrdyMCS3/NCS MCS1/ERRORMCS0/PEREQ MCS2AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 80C186EA PinoutPlcc Package Location with Pin Names Lead Plcc Pinout DiagramQFP Eiaj Pin Names with Package Location QFP Eiaj Package Location with Pin Names Quad Flat Pack Eiaj Pinout DiagramUCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1 Sqfp Pin Functions with Package LocationSqfp Pin Locations with Pin Names Hlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECTCA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Recommended Connections Electrical SpecificationsVoltage on Other Pins with Respect Absolute Maximum RatingsRD/QSMD, UCS, LCS, MCS0/PEREQ DC Specifications 80C186EA/80C188EARD/QSMD, UCS, LCS, MCS0 DC Specifications 80L186EA/80L188EAICC Versus Frequency and Voltage Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation And/or higher temperature will increase delay timeAC Characteristics-80C186EA25/80C186EA20/80C186EA13 AC SpecificationsSRDY, DRQ10 HOLD, PEREQ, ErrorSynchronous Inputs TEST, NMI, INT30 T10IN, ArdyLOCK, RESOUT, Hlda T0OUT, T1OUT AC Characteristics-80L186EA13/80L186EA8ALE, Lock MCS30, LCS, UCSAD150 AD70, ARDY, SRDY, DRQ10 TEST, NMI, INT30, T10IN, ArdyRelative Timings AC Timing Waveforms AC Test ConditionsOutput Delay and Float Waveform Relative Signal Waveform Derating Curves ResetPowerup Reset Waveforms Warm Reset Waveforms Read, Fetch and Refresh Cycle Waveform BUS Cycle WaveformsWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Data Transfer Instruction SET SummaryArithmetic Instruction SET SummaryLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Errata Revision History

80L186EA, 80L188EA, 80C186EA, 80C188EA specifications

The Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA microprocessors represent significant developments in the realm of embedded computing during the 1980s. These processors are part of Intel's x86 architecture, designed to cater to a variety of industrial applications, including automotive and telecommunications.

The 80C188EA and 80C186EA are CMOS variants that offer enhanced power efficiency and reduced heat generation compared to their NMOS predecessors. Operating at clock speeds of up to 25 MHz, these processors are known for their performance in real-time applications. The 80C188EA features a 16-bit data bus and a 16-bit address bus, which can support up to 1 MB of addressable memory. It also boasts an extended instruction set for greater computing flexibility, making it suitable for intricate tasks in embedded systems.

Similarly, the 80C186EA is characterized by its 16-bit architecture, but it includes additional on-chip memory management capabilities. This processor can handle 256 KB of memory directly and supports paged memory management, facilitating efficient multitasking and resource sharing in complex applications. Its integrated DMA controller and interrupt controller allow for superior handling of peripheral devices, making it ideal for real-time processing requirements.

On the other hand, the 80L188EA and 80L186EA are low-power variants optimized for battery-operated designs. These microprocessors are tailored for applications where power consumption is critical. The 80L188EA retains the essential features of the 80C188EA but operates at lower voltage levels, thus allowing for longer operational life in portable devices. The 80L186EA similarly benefits from reduced power consumption, taking advantage of its energy-efficient design to enhance durability in industrial automation scenarios.

All four processors leverage Intel's established x86 architecture, enabling a wide range of software compatibility. Their built-in support for real-time interrupt handling and I/O operations provides developers with valuable tools for building reliable embedded systems. Additionally, they feature on-chip oscillators and timers, further streamlining design requirements and reducing the need for external components.

Overall, the Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA processors are ideal for diverse applications in embedded systems. Their blend of processing power, energy efficiency, and versatility continues to influence the design of modern electronic devices, underscoring Intel's pivotal role in advancing microprocessor technology.
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