Intel 80C188EA, 80L186EA, 80L188EA, 80C186EA specifications Peripheral Control Block Registers

Page 6

80C186EA/80C188EA, 80L186EA/80L188EA

PCB

Function

 

PCB

Function

 

PCB

Function

 

PCB

Function

Offset

 

Offset

 

Offset

 

Offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H

Reserved

 

40H

Reserved

 

80H

Reserved

 

C0H

DMA0 Src. Lo

 

 

 

 

 

 

 

 

 

 

 

02H

Reserved

 

42H

Reserved

 

82H

Reserved

 

C2H

DMA0 Src. Hi

 

 

 

 

 

 

 

 

 

 

 

04H

Reserved

 

44H

Reserved

 

84H

Reserved

 

C4H

DMA0 Dest. Lo

 

 

 

 

 

 

 

 

 

 

 

06H

Reserved

 

46H

Reserved

 

86H

Reserved

 

C6H

DMA0 Dest. Hi

 

 

 

 

 

 

 

 

 

 

 

08H

Reserved

 

48H

Reserved

 

88H

Reserved

 

C8H

DMA0 Count

 

 

 

 

 

 

 

 

 

 

 

0AH

Reserved

 

4AH

Reserved

 

8AH

Reserved

 

CAH

DMA0 Control

 

 

 

 

 

 

 

 

 

 

 

0CH

Reserved

 

4CH

Reserved

 

8CH

Reserved

 

CCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

0EH

Reserved

 

4EH

Reserved

 

8EH

Reserved

 

CEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

10H

Reserved

 

50H

Timer 0 Count

 

90H

Reserved

 

D0H

DMA1 Src. Lo

 

 

 

 

 

 

 

 

 

 

 

12H

Reserved

 

52H

Timer 0 Compare A

 

92H

Reserved

 

D2H

DMA1 Src. Hi

 

 

 

 

 

 

 

 

 

 

 

14H

Reserved

 

54H

Timer 0 Compare B

 

94H

Reserved

 

D4H

DMA1 Dest. Lo

 

 

 

 

 

 

 

 

 

 

 

16H

Reserved

 

56H

Timer 0 Control

 

96H

Reserved

 

D6H

DMA1 Dest. Hi

 

 

 

 

 

 

 

 

 

 

 

18H

Reserved

 

58H

Timer 1 Count

 

98H

Reserved

 

D8H

DMA1 Count

 

 

 

 

 

 

 

 

 

 

 

1AH

Reserved

 

5AH

Timer 1 Compare A

 

9AH

Reserved

 

DAH

DMA1 Control

 

 

 

 

 

 

 

 

 

 

 

1CH

Reserved

 

5CH

Timer 1 Compare B

 

9CH

Reserved

 

DCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

1EH

Reserved

 

5EH

Timer 1 Control

 

9EH

Reserved

 

DEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

20H

Reserved

 

60H

Timer 2 Count

 

A0H

UMCS

 

E0H

Refresh Base

 

 

 

 

 

 

 

 

 

 

 

22H

End of Interrupt

 

62H

Timer 2 Compare

 

A2H

LMCS

 

E2H

Refresh Time

 

 

 

 

 

 

 

 

 

 

 

24H

Poll

 

64H

Reserved

 

A4H

PACS

 

E4H

Refresh Control

 

 

 

 

 

 

 

 

 

 

 

26H

Poll Status

 

66H

Timer 2 Control

 

A6H

MMCS

 

E6H

Reserved

 

 

 

 

 

 

 

 

 

 

 

28H

Interrupt Mask

 

68H

Reserved

 

A8H

MPCS

 

E8H

Reserved

 

 

 

 

 

 

 

 

 

 

 

2AH

Priority Mask

 

6AH

Reserved

 

AAH

Reserved

 

EAH

Reserved

 

 

 

 

 

 

 

 

 

 

 

2CH

In-Service

 

6CH

Reserved

 

ACH

Reserved

 

ECH

Reserved

 

 

 

 

 

 

 

 

 

 

 

2EH

Interrupt Request

 

6EH

Reserved

 

AEH

Reserved

 

EEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

30H

Interrupt Status

 

70H

Reserved

 

B0H

Reserved

 

F0H

Power-Save

 

 

 

 

 

 

 

 

 

 

 

32H

Timer Control

 

72H

Reserved

 

B2H

Reserved

 

F2H

Power Control

 

 

 

 

 

 

 

 

 

 

 

34H

DMA0 Int. Control

 

74H

Reserved

 

B4H

Reserved

 

F4H

Reserved

 

 

 

 

 

 

 

 

 

 

 

36H

DMA1 Int. Control

 

76H

Reserved

 

B6H

Reserved

 

F6H

Step ID

 

 

 

 

 

 

 

 

 

 

 

38H

INT0 Control

 

78H

Reserved

 

B8H

Reserved

 

F8H

Reserved

 

 

 

 

 

 

 

 

 

 

 

3AH

INT1 Control

 

7AH

Reserved

 

BAH

Reserved

 

FAH

Reserved

 

 

 

 

 

 

 

 

 

 

 

3CH

INT2 Control

 

7CH

Reserved

 

BCH

Reserved

 

FCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

3EH

INT3 Control

 

7EH

Reserved

 

BEH

Reserved

 

FEH

Relocation

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Peripheral Control Block Registers

6

6

Image 6
Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Bus Interface Unit Introduction80C186EA Core Architecture Clock GeneratorInterrupt Control Unit Timer/Counter Unit80C186EA Peripheral Architecture Crystal Connection Clock ConnectionPeripheral Control Block Registers Chip-Select Unit Power ManagementDMA Control Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Plcc Package InformationPin Descriptions QFP EiajRWH Resin ClkinOscout ResoutRfsh ALE/QS0BHE RD/QSMDSrdy WR/QS1Ardy DENMCS2 MCS1/ERRORMCS0/PEREQ MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT Sqfp Pin Functions with Package LocationSqfp Pin Locations with Pin Names UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1Package Thermal Specifications 400 600 800 1000 CA PlccCA QFP 60.5 CA Sqfp Absolute Maximum Ratings Electrical SpecificationsVoltage on Other Pins with Respect Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0And/or higher temperature will increase delay time Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation ICC Versus Frequency and VoltageAC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13TEST, NMI, INT30 T10IN, Ardy HOLD, PEREQ, ErrorSynchronous Inputs SRDY, DRQ10MCS30, LCS, UCS AC Characteristics-80L186EA13/80L186EA8ALE, Lock LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 010 DX 010 DL 100 SP101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Revision History Errata