Intel 80L188EA, 80L186EA, 80C188EA, 80C186EA specifications Write Cycle Waveform

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80C186EA/80C188EA, 80L186EA/80L188EA

272432-18

NOTES:

1.During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.

2.Pin names in parentheses apply to the 80C188EA.

Figure 18. Write Cycle Waveform

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Image 37

Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram 80C186EA Core Architecture IntroductionBus Interface Unit Clock Generator80C186EA Peripheral Architecture Timer/Counter UnitInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers DMA Control Unit Power ManagementChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Pin Descriptions Package InformationPlcc QFP EiajRWH Oscout ClkinResin ResoutBHE ALE/QS0Rfsh RD/QSMDArdy WR/QS1Srdy DENMCS0/PEREQ MCS1/ERRORMCS2 MCS3/NCSAD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 80C186EA PinoutPlcc Package Location with Pin Names Lead Plcc Pinout DiagramQFP Eiaj Pin Names with Package Location QFP Eiaj Package Location with Pin Names Quad Flat Pack Eiaj Pinout DiagramSqfp Pin Locations with Pin Names Sqfp Pin Functions with Package LocationHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1400 600 800 1000 CA Plcc Package Thermal SpecificationsCA QFP 60.5 CA Sqfp Voltage on Other Pins with Respect Electrical SpecificationsAbsolute Maximum Ratings Recommended ConnectionsRD/QSMD, UCS, LCS, MCS0/PEREQ DC Specifications 80C186EA/80C188EARD/QSMD, UCS, LCS, MCS0 DC Specifications 80L186EA/80L188EAPdtmr PIN Delay Calculation Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fAnd/or higher temperature will increase delay time ICC Versus Frequency and VoltageAC Characteristics-80C186EA25/80C186EA20/80C186EA13 AC SpecificationsSynchronous Inputs HOLD, PEREQ, ErrorTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10ALE, Lock AC Characteristics-80L186EA13/80L186EA8MCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTAD150 AD70, ARDY, SRDY, DRQ10 TEST, NMI, INT30, T10IN, ArdyRelative Timings AC Timing Waveforms AC Test ConditionsOutput Delay and Float Waveform Relative Signal Waveform Derating Curves Reset Powerup Reset Waveforms Warm Reset Waveforms Read, Fetch and Refresh Cycle Waveform BUS Cycle WaveformsWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Data Transfer Instruction SET SummaryArithmetic Instruction SET SummaryLogic String Manipulation Within seg adding immed to SP 100 SP 010 DX 010 DL101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Errata Revision History