Intel 80L188EA, 80L186EA, 80C188EA WR/QS1, Ardy, Srdy, Den, Dt/R, Lock, Hold, Hlda, Ucs, Lcs

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80C186EA/80C188EA, 80L186EA/80L188EA

 

 

 

 

 

 

 

 

 

 

 

Table 3. Pin Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Pin

Input

Output

Description

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR/QS1

O

 

H(Z)

WRite output signals that data available on the data bus are to be

 

 

 

 

 

 

 

 

 

 

 

R(Z)

written into the accessed memory or I/O device. In Queue Status

 

 

 

 

 

 

 

 

 

 

 

P(1)

Mode, QS1 provides queue status information along with QS0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARDY

I

A(L)

 

Asychronous ReaDY is an input to signal for the end of a bus cycle.

 

 

 

 

 

 

 

 

 

 

S(L)

 

ARDY is asynchronous on rising CLKOUT and synchronous on falling

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT. ARDY or SRDY must be active to terminate any processor

 

 

 

 

 

 

 

 

 

 

 

 

bus cycle, unless they are ignored due to correct programming of the

 

 

 

 

 

 

 

 

 

 

 

 

Chip Select Unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRDY

I

S(L)

 

Synchronous ReaDY is an input to signal for the end of a bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

ARDY or SRDY must be active to terminate any processor bus cycle,

 

 

 

 

 

 

 

 

 

 

 

 

unless they are ignored due to correct programming of the Chip Select

 

 

 

 

 

 

 

 

 

 

 

 

Unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

O

H(Z)

 

Data ENable output to control the enable of bidirectional transceivers

 

 

 

 

 

 

 

 

 

 

R(Z)

 

when buffering a system. DEN is active only when data is to be

 

 

 

 

 

 

 

 

 

 

P(1)

 

transferred on the bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DT/R

O

 

H(Z)

Data Transmit/Receive output controls the direction of a bi-

 

 

 

 

 

 

 

 

 

 

 

R(Z)

directional buffer in a buffered system. DT/R is only available on the

 

 

 

 

 

 

 

 

 

 

 

P(X)

QFP (EIAJ) package and the SQFP package.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

O

 

H(Z)

LOCK output indicates that the bus cycle in progress is not to be

 

 

 

 

 

 

 

 

 

 

 

R(WH)

interrupted. The processor will not service other bus requests (such

 

 

 

 

 

 

 

 

 

 

 

P(1)

as HOLD) while LOCK is active. This pin is configured as a weakly

 

 

 

 

 

 

 

 

 

 

 

 

held high input while RESIN is active and must not be driven low.

 

 

 

 

 

 

 

 

 

 

 

HOLD

I

A(L)

 

HOLD request input to signal that an external bus master wishes to

 

 

 

 

 

 

 

 

 

 

 

 

gain control of the local bus. The processor will relinquish control of

 

 

 

 

 

 

 

 

 

 

 

 

the local bus between instruction boundaries not conditioned by a

 

 

 

 

 

 

 

 

 

 

 

 

LOCK prefix.

 

 

 

 

 

 

 

 

 

 

 

HLDA

O

 

H(1)

HoLD Acknowledge output to indicate that the processor has

 

 

 

 

 

 

 

 

 

 

 

R(0)

relinquished control of the local bus. When HLDA is asserted, the

 

 

 

 

 

 

 

 

 

 

 

P(0)

processor will (or has) floated its data bus and control signals allowing

 

 

 

 

 

 

 

 

 

 

 

 

another bus master to drive the signals directly.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UCS

O

 

H(1)

Upper Chip Select will go active whenever the address of a memory

 

 

 

 

 

 

 

 

 

 

 

R(1)

or I/O bus cycle is within the address limitations programmed by the

 

 

 

 

 

 

 

 

 

 

 

P(1)

user. After reset, UCS is configured to be active for memory accesses

 

 

 

 

 

 

 

 

 

 

 

 

between 0FFC00H and 0FFFFFH. During a processor reset, UCS and

 

 

 

 

 

 

 

 

 

 

 

 

LCS are used to enable ONCE Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LCS

O

 

H(1)

Lower Chip Select will go active whenever the address of a memory

 

 

 

 

 

 

 

 

 

 

 

R(1)

bus cycle is within the address limitations programmed by the user.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

LCS is inactive after a reset. During a processor reset, UCS and LCS

 

 

 

 

 

 

 

 

 

 

 

 

are used to enable ONCE Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram 80C186EA Core Architecture IntroductionBus Interface Unit Clock Generator80C186EA Peripheral Architecture Timer/Counter UnitInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers DMA Control Unit Power ManagementChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Pin Descriptions Package InformationPlcc QFP Eiaj RWH Oscout ClkinResin ResoutBHE ALE/QS0Rfsh RD/QSMDArdy WR/QS1Srdy DENMCS0/PEREQ MCS1/ERRORMCS2 MCS3/NCSAD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 80C186EA PinoutPlcc Package Location with Pin Names Lead Plcc Pinout DiagramQFP Eiaj Pin Names with Package Location QFP Eiaj Package Location with Pin Names Quad Flat Pack Eiaj Pinout DiagramSqfp Pin Locations with Pin Names Sqfp Pin Functions with Package LocationHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1400 600 800 1000 CA Plcc Package Thermal SpecificationsCA QFP 60.5 CA Sqfp Voltage on Other Pins with Respect Electrical SpecificationsAbsolute Maximum Ratings Recommended ConnectionsRD/QSMD, UCS, LCS, MCS0/PEREQ DC Specifications 80C186EA/80C188EARD/QSMD, UCS, LCS, MCS0 DC Specifications 80L186EA/80L188EAPdtmr PIN Delay Calculation Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fAnd/or higher temperature will increase delay time ICC Versus Frequency and VoltageAC Characteristics-80C186EA25/80C186EA20/80C186EA13 AC SpecificationsSynchronous Inputs HOLD, PEREQ, ErrorTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10ALE, Lock AC Characteristics-80L186EA13/80L186EA8MCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTAD150 AD70, ARDY, SRDY, DRQ10 TEST, NMI, INT30, T10IN, ArdyRelative Timings AC Timing Waveforms AC Test ConditionsOutput Delay and Float Waveform Relative Signal Waveform Derating Curves ResetPowerup Reset Waveforms Warm Reset Waveforms Read, Fetch and Refresh Cycle Waveform BUS Cycle WaveformsWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Data Transfer Instruction SET SummaryArithmetic Instruction SET SummaryLogic String Manipulation Within seg adding immed to SP 100 SP 010 DX 010 DL101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Errata Revision History
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