Intel 80L186EA, 80L188EA, 80C188EA, 80C186EA specifications Within seg adding immed to SP

Page 48

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

 

 

 

 

 

80C186EA

80C188EA

 

Function

 

Format

 

 

Clock

Clock

Comments

 

 

 

 

 

Cycles

Cycles

 

CONTROL TRANSFER (Continued)

 

 

 

 

 

 

 

RET e Return from CALL:

 

 

 

 

 

 

 

Within segment

1 1 0 0 0 0 1 1

 

 

16

20

 

 

 

 

 

 

 

 

 

Within seg adding immed to SP

1 1 0 0 0 0 1 0

data-low

data-high

18

22

 

 

 

 

 

 

 

 

 

Intersegment

1 1 0 0 1 0 1 1

 

 

22

30

 

 

 

 

 

 

 

 

 

Intersegment adding immediate to SP

1 1 0 0 1 0 1 0

data-low

data-high

25

33

 

JE/JZ e Jump on equal/zero

 

 

 

 

 

 

 

0 1 1 1 0 1 0 0

disp

 

4/13

4/13

JMP not

JL/JNGE e Jump on less/not greater or equal

 

 

 

 

 

 

taken/JMP

0 1 1 1 1 1 0 0

disp

 

4/13

4/13

 

taken

JLE/JNG e Jump on less or equal/not greater

 

 

 

 

 

 

0 1 1 1 1 1 1 0

disp

 

4/13

4/13

 

JB/JNAE e Jump on below/not above or equal

0 1 1 1 0 0 1 0

disp

 

4/13

4/13

 

JBE/JNA e Jump on below or equal/not above

0 1 1 1 0 1 1 0

disp

 

4/13

4/13

 

JP/JPE e Jump on parity/parity even

0 1 1 1 1 0 1 0

disp

 

4/13

4/13

 

JO e Jump on overflow

0 1 1 1 0 0 0 0

disp

 

4/13

4/13

 

JS e Jump on sign

0 1 1 1 1 0 0 0

disp

 

4/13

4/13

 

JNE/JNZ e Jump on not equal/not zero

0 1 1 1 0 1 0 1

disp

 

4/13

4/13

 

JNL/JGE e Jump on not less/greater or equal

0 1 1 1 1 1 0 1

disp

 

4/13

4/13

 

JNLE/JG e Jump on not less or equal/greater

0 1 1 1 1 1 1 1

disp

 

4/13

4/13

 

JNB/JAE e Jump on not below/above or equal

0 1 1 1 0 0 1 1

disp

 

4/13

4/13

 

JNBE/JA e Jump on not below or equal/above

0 1 1 1 0 1 1 1

disp

 

4/13

4/13

 

JNP/JPO e Jump on not par/par odd

0 1 1 1 1 0 1 1

disp

 

4/13

4/13

 

JNO e Jump on not overflow

0 1 1 1 0 0 0 1

disp

 

4/13

4/13

 

JNS e Jump on not sign

0 1 1 1 1 0 0 1

disp

 

4/13

4/13

 

JCXZ e Jump on CX zero

1 1 1 0 0 0 1 1

disp

 

5/15

5/15

 

LOOP e Loop CX times

1 1 1 0 0 0 1 0

disp

 

6/16

6/16

LOOP not

LOOPZ/LOOPE e Loop while zero/equal

 

 

 

 

 

 

taken/LOOP

1 1 1 0 0 0 0 1

disp

 

6/16

6/16

 

taken

LOOPNZ/LOOPNE e Loop while not zero/equal

 

 

 

 

 

 

1 1 1 0 0 0 0 0

disp

 

6/16

6/16

 

 

 

 

 

 

 

 

 

ENTER e Enter Procedure

1 1 0 0 1 0 0 0

data-low

data-high

L

 

 

 

L e 0

 

 

 

15

19

 

L e 1

 

 

 

25

29

 

L l 1

 

 

 

 

22a16(nb1)

26a20(nb1)

 

LEAVE e Leave Procedure

1 1 0 0 1 0 0 1

 

 

8

8

 

INT e Interrupt:

 

 

 

 

 

 

 

Type specified

1 1 0 0 1 1 0 1

type

 

47

47

 

 

 

 

 

 

 

 

Type 3

1 1 0 0 1 1 0 0

 

 

45

45

if INT. taken/

INTO e Interrupt on overflow

 

 

 

 

 

 

if INT. not

1 1 0 0 1 1 1 0

 

 

48/4

48/4

 

 

taken

 

 

 

 

 

 

 

IRET e Interrupt return

1 1 0 0 1 1 1 1

28

28

BOUND e Detect value out of range

0 1 1 0 0 0 1 0

mod reg r/m

33 – 35

33 – 35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

48

48

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Introduction 80C186EA Core ArchitectureBus Interface Unit Clock GeneratorTimer/Counter Unit 80C186EA Peripheral ArchitectureInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers Power Management DMA Control UnitChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Package Information Pin DescriptionsPlcc QFP EiajRWH Clkin OscoutResin ResoutALE/QS0 BHERfsh RD/QSMDWR/QS1 ArdySrdy DENMCS1/ERROR MCS0/PEREQMCS2 MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesSqfp Pin Functions with Package Location Sqfp Pin Locations with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1Package Thermal Specifications 400 600 800 1000 CA PlccCA QFP 60.5 CA Sqfp Electrical Specifications Voltage on Other Pins with RespectAbsolute Maximum Ratings Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c f Pdtmr PIN Delay CalculationAnd/or higher temperature will increase delay time ICC Versus Frequency and VoltageAC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13HOLD, PEREQ, Error Synchronous InputsTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10AC Characteristics-80L186EA13/80L186EA8 ALE, LockMCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data Transfer Instruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 010 DX 010 DL 100 SP101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Revision History Errata
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