Intel 80L188EA, 80L186EA, 80C188EA, 80C186EA specifications Relative Timings

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS (Continued)

Relative Timings (80C186EA25/20/13, 80L186EA13/8)

Symbol		Parameter	Min	Max	Unit	Notes
RELATIVE TIMINGS
TLHLL	ALE Rising to ALE Falling		T b 15		ns
TAVLL	Address Valid to ALE Falling		(/2T b 10		ns
TPLLL	Chip Selects Valid to ALE Falling		(/2T b 10		ns	1
TLLAX	Address Hold from ALE Falling		(/2T b 10		ns
			(/2T b 15
TLLWL	ALE Falling to WR Falling				ns	1
			(/2T b 15
TLLRL	ALE Falling to RD Falling				ns	1
			(/2T b 10
TRHLH	RD Rising to ALE Rising				ns	1
			(/2T b 10
TWHLH	WR Rising to ALE Rising				ns	1
TAFRL	Address Float to RD Falling		0		ns
			(2*T) b 5
TRLRH	RD Falling to RD Rising				ns	2
			(2*T) b 5
TWLWH	WR Falling to WR Rising				ns	2
			T b 15
TRHAV	RD Rising to Address Active				ns
			T b 15
TWHDX	Output Data Hold after WR Rising				ns
			(/2T b 10
TWHDEX	WR Rising to DEN Rising				ns	1
			(/2T b 10
TWHPH	WR Rising to Chip Select Rising				ns	1, 4
			(/2T b 10
TRHPH	RD Rising to Chip Select Rising				ns	1, 4
			(/2T b 10
TPHPL	CS Inactive to CS Active				ns	1
TDXDL	DEN Inactive to DT/R Low		0		ns	5
TOVRH	ONCE (UCS, LCS) Active to RESIN Rising		T		ns	3
TRHOX	ONCE (UCS, LCS) to RESIN Rising		T		ns	3

NOTES:

1.Assumes equal loading on both pins.

2.Can be extended using wait states.

3.Not tested.

4.Not applicable to latched A2:1. These signals change only on falling T1.

5.For write cycle followed by read cycle.

6.Operating conditions for 25 MHz are 0§C to a70§C, VCC e 5.0V g10%.

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