Intel 80L186EA, 80L188EA, 80C188EA, 80C186EA specifications Instruction SET Summary, Data Transfer

Page 44

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY

 

 

 

 

 

80C186EA

80C188EA

 

Function

 

Format

 

Clock

Clock

Comments

 

 

 

 

 

Cycles

Cycles

 

DATA TRANSFER

 

 

 

 

 

 

 

MOV e Move:

 

 

 

 

 

 

 

Register to Register/Memory

1 0 0 0 1 0 0 w

mod reg r/m

 

 

2/12

2/12*

 

 

 

 

 

 

 

 

 

Register/memory to register

1 0 0 0 1 0 1 w

mod reg r/m

 

 

2/9

2/9

 

 

 

 

 

 

 

 

 

Immediate to register/memory

1 1 0 0 0 1 1 w

mod 000 r/m

data

data if we1

12 – 13

12 – 13

8/16-bit

 

 

 

 

 

 

 

 

Immediate to register

1 0 1 1 w reg

data

data if we1

 

3 – 4

3 – 4

8/16-bit

Memory to accumulator

1 0 1 0 0 0 0 w

addr-low

addr-high

 

8

8*

 

 

 

 

 

 

 

9*

 

Accumulator to memory

1 0 1 0 0 0 1 w

addr-low

addr-high

 

9

 

 

 

 

 

 

 

 

 

Register/memory to segment register

1 0 0 0 1 1 1 0

mod 0 reg r/m

 

 

2/9

2/13

 

 

 

 

 

 

 

 

 

Segment register to register/memory

1 0 0 0 1 1 0 0

mod 0 reg r/m

 

 

2/11

2/15

 

PUSH e Push:

 

 

 

 

 

 

 

Memory

1 1 1 1 1 1 1 1

mod 1 1 0 r/m

 

 

16

20

 

 

 

 

 

 

 

 

 

Register

0 1 0 1 0 reg

 

 

 

10

14

 

 

 

 

 

 

 

 

 

Segment register

0 0 0 reg 1 1 0

 

 

 

9

13

 

 

 

 

 

 

 

 

 

Immediate

0 1 1 0 1 0 s 0

data

data if se0

 

10

14

 

 

 

 

 

 

 

 

 

PUSHA e Push All

0 1 1 0 0 0 0 0

 

 

 

36

68

 

POP e Pop:

 

 

 

 

 

 

 

Memory

1 0 0 0 1 1 1 1

mod 0 0 0 r/m

 

 

20

24

 

 

 

 

 

 

 

 

 

Register

0 1 0 1 1 reg

 

 

 

10

14

 

 

 

(reg i 01)

 

 

 

 

 

Segment register

0 0 0 reg 1 1 1

 

 

8

12

 

 

 

 

 

 

 

 

 

POPA e Pop All

0 1 1 0 0 0 0 1

 

 

 

51

83

 

XCHG e Exchange:

 

 

 

 

 

 

 

Register/memory with register

1 0 0 0 0 1 1 w

mod reg r/m

 

 

4/17

4/17*

 

 

 

 

 

 

 

 

 

Register with accumulator

1 0 0 1 0 reg

 

 

 

3

3

 

IN e Input from:

 

 

 

 

 

 

 

Fixed port

1 1 1 0 0 1 0 w

port

 

 

10

10*

 

 

 

 

 

 

 

7*

 

Variable port

1 1 1 0 1 1 0 w

 

 

 

8

 

OUT e Output to:

 

 

 

 

 

 

 

Fixed port

1 1 1 0 0 1 1 w

port

 

 

9

9*

 

 

 

 

 

 

 

7*

 

Variable port

1 1 1 0 1 1 1 w

 

 

 

7

 

XLAT e Translate byte to AL

1 1 0 1 0 1 1 1

11

15

LEA e Load EA to register

1 0 0 0 1 1 0 1

mod reg r/m

6

6

LDS e Load pointer to DS

1 1 0 0 0 1 0 1

mod reg r/m

(mod i 11)

18

26

LES e Load pointer to ES

1 1 0 0 0 1 0 0

mod reg r/m

(mod i 11)

18

26

LAHF e Load AH with flags

1 0 0 1 1 1 1 1

2

2

SAHF e Store AH into flags

1 0 0 1 1 1 1 0

3

3

PUSHF e Push flags

1 0 0 1 1 1 0 0

9

13

POPF e Pop flags

1 0 0 1 1 1 0 1

8

12

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Introduction 80C186EA Core ArchitectureBus Interface Unit Clock GeneratorTimer/Counter Unit 80C186EA Peripheral ArchitectureInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers Power Management DMA Control UnitChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Package Information Pin DescriptionsPlcc QFP EiajRWH Clkin OscoutResin ResoutALE/QS0 BHERfsh RD/QSMDWR/QS1 ArdySrdy DENMCS1/ERROR MCS0/PEREQMCS2 MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesSqfp Pin Functions with Package Location Sqfp Pin Locations with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1CA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Electrical Specifications Voltage on Other Pins with RespectAbsolute Maximum Ratings Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c f Pdtmr PIN Delay CalculationAnd/or higher temperature will increase delay time ICC Versus Frequency and VoltageAC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13HOLD, PEREQ, Error Synchronous InputsTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10AC Characteristics-80L186EA13/80L186EA8 ALE, LockMCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Revision History Errata

80L186EA, 80L188EA, 80C186EA, 80C188EA specifications

The Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA microprocessors represent significant developments in the realm of embedded computing during the 1980s. These processors are part of Intel's x86 architecture, designed to cater to a variety of industrial applications, including automotive and telecommunications.

The 80C188EA and 80C186EA are CMOS variants that offer enhanced power efficiency and reduced heat generation compared to their NMOS predecessors. Operating at clock speeds of up to 25 MHz, these processors are known for their performance in real-time applications. The 80C188EA features a 16-bit data bus and a 16-bit address bus, which can support up to 1 MB of addressable memory. It also boasts an extended instruction set for greater computing flexibility, making it suitable for intricate tasks in embedded systems.

Similarly, the 80C186EA is characterized by its 16-bit architecture, but it includes additional on-chip memory management capabilities. This processor can handle 256 KB of memory directly and supports paged memory management, facilitating efficient multitasking and resource sharing in complex applications. Its integrated DMA controller and interrupt controller allow for superior handling of peripheral devices, making it ideal for real-time processing requirements.

On the other hand, the 80L188EA and 80L186EA are low-power variants optimized for battery-operated designs. These microprocessors are tailored for applications where power consumption is critical. The 80L188EA retains the essential features of the 80C188EA but operates at lower voltage levels, thus allowing for longer operational life in portable devices. The 80L186EA similarly benefits from reduced power consumption, taking advantage of its energy-efficient design to enhance durability in industrial automation scenarios.

All four processors leverage Intel's established x86 architecture, enabling a wide range of software compatibility. Their built-in support for real-time interrupt handling and I/O operations provides developers with valuable tools for building reliable embedded systems. Additionally, they feature on-chip oscillators and timers, further streamlining design requirements and reducing the need for external components.

Overall, the Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA processors are ideal for diverse applications in embedded systems. Their blend of processing power, energy efficiency, and versatility continues to influence the design of modern electronic devices, underscoring Intel's pivotal role in advancing microprocessor technology.
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