Intel 80L188EA, 80L186EA, 80C188EA, 80C186EA specifications Instruction SET Summary, Arithmetic

Page 45

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

 

 

 

 

 

 

80C186EA

80C188EA

 

Function

 

Format

 

 

Clock

Clock

Comments

 

 

 

 

 

 

Cycles

Cycles

 

DATA TRANSFER (Continued)

 

 

 

 

 

 

 

 

SEGMENT e Segment Override:

 

 

 

 

 

 

 

 

CS

0 0 1 0 1 1 1 0

 

 

 

 

2

2

 

 

 

 

 

 

 

 

 

 

SS

0 0 1 1 0 1 1 0

 

 

 

 

2

2

 

 

 

 

 

 

 

 

 

 

DS

0 0 1 1 1 1 1 0

 

 

 

 

2

2

 

 

 

 

 

 

 

 

 

 

ES

0 0 1 0 0 1 1 0

 

 

 

 

2

2

 

ARITHMETIC

 

 

 

 

 

 

 

 

ADD e Add:

 

 

 

 

 

 

 

 

Reg/memory with register to either

0 0 0 0 0 0 d w

mod reg r/m

 

 

 

3/10

3/10*

 

 

 

 

 

 

 

 

4/16*

 

Immediate to register/memory

1 0 0 0 0 0 s w

mod 0 0 0 r/m

data

data if s we01

 

4/16

 

 

 

 

 

 

 

 

 

 

Immediate to accumulator

0 0 0 0 0 1 0 w

data

data if we1

 

 

3/4

3/4

8/16-bit

ADC e Add with carry:

 

 

 

 

 

 

 

 

Reg/memory with register to either

0 0 0 1 0 0 d w

mod reg r/m

 

 

 

3/10

3/10*

 

 

 

 

 

 

 

 

4/16*

 

Immediate to register/memory

1 0 0 0 0 0 s w

mod 0 1 0 r/m

data

data if s we01

 

4/16

 

 

 

 

 

 

 

 

 

 

Immediate to accumulator

0 0 0 1 0 1 0 w

data

data if we1

 

 

3/4

3/4

8/16-bit

INC e Increment:

 

 

 

 

 

 

 

 

Register/memory

1 1 1 1 1 1 1 w

mod 0 0 0 r/m

 

 

 

3/15

3/15*

 

 

 

 

 

 

 

 

 

 

Register

0 1 0 0 0 reg

 

 

 

 

3

3

 

SUB e Subtract:

 

 

 

 

 

 

 

 

Reg/memory and register to either

0 0 1 0 1 0 d w

mod reg r/m

 

 

 

3/10

3/10*

 

 

 

 

 

 

 

 

4/16*

 

Immediate from register/memory

1 0 0 0 0 0 s w

mod 1 0 1 r/m

data

data if s we01

 

4/16

 

 

 

 

 

 

 

 

 

 

Immediate from accumulator

0 0 1 0 1 1 0 w

data

data if we1

 

 

3/4

3/4

8/16-bit

SBB e Subtract with borrow:

 

 

 

 

 

 

 

 

Reg/memory and register to either

0 0 0 1 1 0 d w

mod reg r/m

 

 

 

3/10

3/10*

 

 

 

 

 

 

 

 

4/16*

 

Immediate from register/memory

1 0 0 0 0 0 s w

mod 0 1 1 r/m

data

data if s we01

 

4/16

 

Immediate from accumulator

0 0 0 1 1 1 0 w

data

data if we1

 

 

3/4

3/4*

8/16-bit

DEC e Decrement

 

 

 

 

 

 

 

 

Register/memory

1 1 1 1 1 1 1 w

mod 0 0 1 r/m

 

 

 

3/15

3/15*

 

 

 

 

 

 

 

 

 

 

Register

0 1 0 0 1 reg

 

 

 

 

3

3

 

CMP e Compare:

 

 

 

 

 

 

 

 

Register/memory with register

0 0 1 1 1 0 1 w

mod reg r/m

 

 

 

3/10

3/10*

 

 

 

 

 

 

 

 

3/10*

 

Register with register/memory

0 0 1 1 1 0 0 w

mod reg r/m

 

 

 

3/10

 

 

 

 

 

 

 

 

3/10*

 

Immediate with register/memory

1 0 0 0 0 0 s w

mod 1 1 1 r/m

data

data if s we01

 

3/10

 

 

 

 

 

 

 

 

 

 

Immediate with accumulator

0 0 1 1 1 1 0 w

data

data if we1

 

 

3/4

3/4

8/16-bit

NEG e Change sign register/memory

1 1 1 1 0 1 1 w

mod 0 1 1 r/m

 

 

 

3/10*

3/10*

 

AAA e ASCII adjust for add

0 0 1 1 0 1 1 1

 

 

 

 

8

8

 

DAA e Decimal adjust for add

0 0 1 0 0 1 1 1

 

 

 

 

4

4

 

AAS e ASCII adjust for subtract

0 0 1 1 1 1 1 1

 

 

 

 

7

7

 

DAS e Decimal adjust for subtract

0 0 1 0 1 1 1 1

 

 

 

 

4

4

 

MUL e Multiply (unsigned):

 

 

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 100 r/m

 

 

 

 

 

 

Register-Byte

 

 

 

 

 

26 – 28

26 – 28

 

Register-Word

 

 

 

 

 

35 – 37

35 – 37

 

Memory-Byte

 

 

 

 

 

32 – 34

32 – 34

 

Memory-Word

 

 

 

 

 

41 – 43

41 – 48*

 

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram 80C186EA Core Architecture IntroductionBus Interface Unit Clock Generator80C186EA Peripheral Architecture Timer/Counter UnitInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers DMA Control Unit Power ManagementChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Pin Descriptions Package InformationPlcc QFP EiajRWH Oscout ClkinResin ResoutBHE ALE/QS0Rfsh RD/QSMDArdy WR/QS1Srdy DENMCS0/PEREQ MCS1/ERRORMCS2 MCS3/NCSAD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 80C186EA PinoutPlcc Package Location with Pin Names Lead Plcc Pinout DiagramQFP Eiaj Pin Names with Package Location QFP Eiaj Package Location with Pin Names Quad Flat Pack Eiaj Pinout DiagramSqfp Pin Locations with Pin Names Sqfp Pin Functions with Package LocationHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1Package Thermal Specifications 400 600 800 1000 CA PlccCA QFP 60.5 CA Sqfp Voltage on Other Pins with Respect Electrical SpecificationsAbsolute Maximum Ratings Recommended ConnectionsRD/QSMD, UCS, LCS, MCS0/PEREQ DC Specifications 80C186EA/80C188EARD/QSMD, UCS, LCS, MCS0 DC Specifications 80L186EA/80L188EAPdtmr PIN Delay Calculation Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fAnd/or higher temperature will increase delay time ICC Versus Frequency and VoltageAC Characteristics-80C186EA25/80C186EA20/80C186EA13 AC SpecificationsSynchronous Inputs HOLD, PEREQ, ErrorTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10ALE, Lock AC Characteristics-80L186EA13/80L186EA8MCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTAD150 AD70, ARDY, SRDY, DRQ10 TEST, NMI, INT30, T10IN, ArdyRelative Timings AC Timing Waveforms AC Test ConditionsOutput Delay and Float Waveform Relative Signal Waveform Derating Curves ResetPowerup Reset Waveforms Warm Reset Waveforms Read, Fetch and Refresh Cycle Waveform BUS Cycle WaveformsWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Data Transfer Instruction SET SummaryArithmetic Instruction SET SummaryLogic String Manipulation Within seg adding immed to SP 010 DX 010 DL 100 SP101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Errata Revision History

80L186EA, 80L188EA, 80C186EA, 80C188EA specifications

The Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA microprocessors represent significant developments in the realm of embedded computing during the 1980s. These processors are part of Intel's x86 architecture, designed to cater to a variety of industrial applications, including automotive and telecommunications.

The 80C188EA and 80C186EA are CMOS variants that offer enhanced power efficiency and reduced heat generation compared to their NMOS predecessors. Operating at clock speeds of up to 25 MHz, these processors are known for their performance in real-time applications. The 80C188EA features a 16-bit data bus and a 16-bit address bus, which can support up to 1 MB of addressable memory. It also boasts an extended instruction set for greater computing flexibility, making it suitable for intricate tasks in embedded systems.

Similarly, the 80C186EA is characterized by its 16-bit architecture, but it includes additional on-chip memory management capabilities. This processor can handle 256 KB of memory directly and supports paged memory management, facilitating efficient multitasking and resource sharing in complex applications. Its integrated DMA controller and interrupt controller allow for superior handling of peripheral devices, making it ideal for real-time processing requirements.

On the other hand, the 80L188EA and 80L186EA are low-power variants optimized for battery-operated designs. These microprocessors are tailored for applications where power consumption is critical. The 80L188EA retains the essential features of the 80C188EA but operates at lower voltage levels, thus allowing for longer operational life in portable devices. The 80L186EA similarly benefits from reduced power consumption, taking advantage of its energy-efficient design to enhance durability in industrial automation scenarios.

All four processors leverage Intel's established x86 architecture, enabling a wide range of software compatibility. Their built-in support for real-time interrupt handling and I/O operations provides developers with valuable tools for building reliable embedded systems. Additionally, they feature on-chip oscillators and timers, further streamlining design requirements and reducing the need for external components.

Overall, the Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA processors are ideal for diverse applications in embedded systems. Their blend of processing power, energy efficiency, and versatility continues to influence the design of modern electronic devices, underscoring Intel's pivotal role in advancing microprocessor technology.
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