Intel 80C188EA, 80L186EA, 80L188EA, 80C186EA specifications Halt Cycle Waveform

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80C186EA/80C188EA, 80L186EA/80L188EA

272432 – 19

NOTES:

1.The processor drives these pins to 0 during Idle and Powerdown Modes.

2.Pin names in parentheses apply to the 80C188EA.

Figure 19. Halt Cycle Waveform

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Image 38

Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Bus Interface Unit Introduction80C186EA Core Architecture Clock GeneratorInterrupt Control Unit Timer/Counter Unit80C186EA Peripheral Architecture Crystal Connection Clock ConnectionPeripheral Control Block Registers Chip-Select Unit Power ManagementDMA Control Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Plcc Package InformationPin Descriptions QFP EiajRWH Resin ClkinOscout ResoutRfsh ALE/QS0BHE RD/QSMDSrdy WR/QS1Ardy DENMCS2 MCS1/ERRORMCS0/PEREQ MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT Sqfp Pin Functions with Package LocationSqfp Pin Locations with Pin Names UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1CA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Absolute Maximum Ratings Electrical SpecificationsVoltage on Other Pins with Respect Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0And/or higher temperature will increase delay time Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation ICC Versus Frequency and VoltageAC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13TEST, NMI, INT30 T10IN, Ardy HOLD, PEREQ, ErrorSynchronous Inputs SRDY, DRQ10MCS30, LCS, UCS AC Characteristics-80L186EA13/80L186EA8ALE, Lock LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Revision History Errata