Intel 80C188EA MCS0/PEREQ, MCS1/ERROR, MCS2, MCS3/NCS, PCS5/A1, PCS6/A2, T0OUT, T1OUT, T0IN, T1IN

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80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

 

 

 

 

Pin

Pin

Input

Output

Description

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCS0/PEREQ

I/O

A(L)

H(1)

These pins provide a multiplexed function. If enabled,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

these pins normally comprise a block of Mid-Range Chip

 

MCS1/ERROR

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select outputs which will go active whenever the address

 

MCS2

 

 

 

 

 

P(1)

 

 

 

of a memory bus cycle is within the address limitations

 

MCS3/NCS

 

 

 

 

 

 

 

programmed by the user. In Numerics Mode (80C186EA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

only), three of the pins become handshaking pins for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80C187. The CoProcessor REQuest input signals that a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data transfer is pending. ERROR is an input which

 

 

 

 

 

 

 

 

 

 

 

 

 

 

indicates that the previous numerics coprocessor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation resulted in an exception condition. An interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type 16 is generated when ERROR is sampled active at

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the beginning of a numerics operation. Numerics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coprocessor Select is an output signal generated when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the processor accesses the 80C187.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS4:0

O

 

H(1)

Peripheral Chip Selects go active whenever the address

 

 

 

 

 

 

 

 

 

 

 

 

 

R(1)

of a memory or I/O bus cycle is within the address

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

limitations programmed by the user.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS5/A1

O

 

H(1)/H(X)

These pins provide a multiplexed function. As additional

 

 

 

 

 

 

 

 

 

Peripheral Chip Selects, they go active whenever the

 

PCS6/A2

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

address of a memory or I/O bus cycle is within the

 

 

 

 

 

 

 

 

 

 

 

 

 

address limitations by the user. They may also be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

programmed to provide latched Address A2:1 signals.

 

 

 

 

 

 

 

 

 

 

T0OUT

O

 

H(Q)

Timer OUTput pins can be programmed to provide a

 

T1OUT

 

 

R(1)

single clock or continuous waveform generation,

 

 

 

 

 

 

 

 

 

 

 

 

 

P(Q)

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0IN

I

A(L)

 

Timer INput is used either as clock or control signals,

 

T1IN

 

A(E)

 

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

DRQ0

I

A(L)

 

DMA ReQuest is asserted by an external request when it

 

DRQ1

 

 

 

is prepared for a DMA transfer.

 

 

 

 

 

 

 

 

 

 

INT0

 

 

I

A(E,L)

 

Maskable INTerrupt input will cause a vector to a specific

 

INT1/SELECT

 

 

 

Type interrupt routine. To allow interrupt expansion, INT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and/or INT1 can be used with INTA0 and INTA1 to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interface with an external slave controller. INT1 becomes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SELECT when the ICU is configured for Slave Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT2/INTA0

I/O

A(E,L)

H(1)

These pins provide multiplexed functions. As inputs, they

 

 

 

 

 

 

 

provide a maskable INTerrupt that will cause the CPU to

 

INT3/INTA1/IRQ

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

vector to a specific Type interrupt routine. As outputs,

 

 

 

 

 

 

 

 

 

 

 

 

 

each is programmatically controlled to provide an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTerrupt Acknowledge handshake signal to allow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupt expansion. INT3/INTA1 becomes IRQ when the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICU is configured for Slave Mode.

 

 

 

 

 

 

 

N.C.

 

 

 

No Connect. For compatibility with future products, do not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect to these pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Bus Interface Unit Introduction80C186EA Core Architecture Clock GeneratorInterrupt Control Unit Timer/Counter Unit80C186EA Peripheral Architecture Crystal Connection Clock ConnectionPeripheral Control Block Registers Chip-Select Unit Power ManagementDMA Control Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Plcc Package InformationPin Descriptions QFP EiajRWH Resin Clkin Oscout ResoutRfsh ALE/QS0BHE RD/QSMDSrdy WR/QS1Ardy DENMCS2 MCS1/ERRORMCS0/PEREQ MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT Sqfp Pin Functions with Package LocationSqfp Pin Locations with Pin Names UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1CA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Absolute Maximum Ratings Electrical SpecificationsVoltage on Other Pins with Respect Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0And/or higher temperature will increase delay time Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation ICC Versus Frequency and VoltageAC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13TEST, NMI, INT30 T10IN, Ardy HOLD, PEREQ, ErrorSynchronous Inputs SRDY, DRQ10MCS30, LCS, UCS AC Characteristics-80L186EA13/80L186EA8ALE, Lock LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Revision History Errata
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