Intel 80L186EA Introduction, 80C186EA Core Architecture, Bus Interface Unit, Clock Generator

80C186EA/80C188EA, 80L186EA/80L188EA

INTRODUCTION

Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physi- cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.

The 80C186EA is the second product in a new gen- eration of low-power, high-integration microproces- sors. It enhances the existing 80C186XL family by offering new features and operating modes. The 80C186EA is object code compatible with the 80C186XL embedded processor.

The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the

80C186EA embedded processor. Current 80C186EA customers can easily upgrade their de- signs to use the 80L186EA and benefit from the re- duced power consumption inherent in 3V operation.

The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical applications. Low-power applications benefit from the static de- sign of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space-critical applications benefit from the inte- gration of commonly used system peripherals. Two flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generat- ed from the on-chip peripherals. Three general pur- pose timer/counters round out the feature set of the 80C186EA.

Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static opera- tion. The Bus Interface Unit (BIU) is the same as that found on the original 80C186 family products. An independent internal bus is used to allow communi- cation between the BIU and internal peripherals.

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80C186EA CORE ARCHITECTURE

Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. It is also responsible for reading data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates two control signals (DEN and DT/R) when interfacing to exter- nal transceiver chips. This capability allows the addi- tion of transceivers for simple buffering of the mulit- plexed address/data bus.

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes.

The oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscilla- tor circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components. All AC timings are referenced to

CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range:	Application Specific
ESR (Equivalent Series Resistance):		60X max
C0 (Shunt Capacitance of Crystal):		7.0 pF max
CL (Load Capacitance):		20 pF g 2 pF
Drive Level:		2 mW max

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