Intel 80C186EA, 80L186EA, 80L188EA, 80C188EA specifications Warm Reset Waveforms

Page 35

Figure 16. Warm Reset Waveforms

35

35

272432 – 16

NOTES:

1.CLKOUT resynchronization occurs approximately 1(/2 CLKIN periods after RESIN is sampled low. If RESIN is sampled low while CLKOUT is transitioning high, then CLKOUT will remain high for two CLKIN periods. If RESIN is sampled low while CLKOUT is transitioning high, then CLKOUT will not be affected.

2.Pin names in parentheses apply to the 80C188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Image 35

Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Clock Generator Introduction80C186EA Core Architecture Bus Interface UnitCrystal Connection Clock Connection Timer/Counter Unit80C186EA Peripheral Architecture Interrupt Control UnitPeripheral Control Block Registers Refresh Control Unit Power ManagementDMA Control Unit Chip-Select UnitDifferences Between the 80C186XL and the 80C186EA QFP Eiaj Package InformationPin Descriptions PlccRWH Resout ClkinOscout ResinRD/QSMD ALE/QS0BHE RfshDEN WR/QS1Ardy SrdyMCS3/NCS MCS1/ERRORMCS0/PEREQ MCS2AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 80C186EA PinoutPlcc Package Location with Pin Names Lead Plcc Pinout DiagramQFP Eiaj Pin Names with Package Location QFP Eiaj Package Location with Pin Names Quad Flat Pack Eiaj Pinout DiagramUCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1 Sqfp Pin Functions with Package LocationSqfp Pin Locations with Pin Names Hlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECTCA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Recommended Connections Electrical SpecificationsVoltage on Other Pins with Respect Absolute Maximum RatingsRD/QSMD, UCS, LCS, MCS0/PEREQ DC Specifications 80C186EA/80C188EARD/QSMD, UCS, LCS, MCS0 DC Specifications 80L186EA/80L188EAICC Versus Frequency and Voltage Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation And/or higher temperature will increase delay timeAC Characteristics-80C186EA25/80C186EA20/80C186EA13 AC SpecificationsSRDY, DRQ10 HOLD, PEREQ, ErrorSynchronous Inputs TEST, NMI, INT30 T10IN, ArdyLOCK, RESOUT, Hlda T0OUT, T1OUT AC Characteristics-80L186EA13/80L186EA8ALE, Lock MCS30, LCS, UCSAD150 AD70, ARDY, SRDY, DRQ10 TEST, NMI, INT30, T10IN, ArdyRelative Timings AC Timing Waveforms AC Test ConditionsOutput Delay and Float Waveform Relative Signal Waveform Derating Curves ResetPowerup Reset Waveforms Warm Reset Waveforms Read, Fetch and Refresh Cycle Waveform BUS Cycle WaveformsWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Data Transfer Instruction SET SummaryArithmetic Instruction SET SummaryLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Errata Revision History