Intel 80C186EA, 80C188EA DC Specifications 80L186EA/80L188EA, RD/QSMD, UCS, LCS, MCS0

80C186EA/80C188EA, 80L186EA/80L188EA

DC SPECIFICATIONS (80L186EA/80L188EA)

Symbol		Parameter	Min	Max	Units	Conditions
VCC	Supply Voltage		2.7	5.5	V
VIL	Input Low Voltage for All Pins		b0.5	0.3 VCC	V
VIH	Input High Voltage for All Pins		0.7 VCC	VCC a 0.5	V
VOL	Output Low Voltage			0.45	V	IOL e 1.6 mA (min)
VOH	Output High Voltage		VCC b 0.5		V	IOH e b1 mA (min)
VHYR	Input Hysterisis on RESIN		0.30		V
IIL1	Input Leakage Current (except			g10	mA	0V s VIN s VCC
	RD/QSMD, UCS, LCS, MCS0/PEREQ,
	MCS1, LOCK and TEST)
IIL2	Input Leakage Current		b275		mA	VIN e 0.7 VCC
	(RD/QSMD, UCS, LCS, MCS0,					(Note 1)
	MCS1, LOCK and TEST)
IOL	Output Leakage Current			g10	mA	0.45 s VOUT s VCC
						(Note 2)
ICC5	Supply Current (RESET, 5.5V)
	80L186EA-13			65	mA	(Note 3)
	80L186EA-8			40	mA	(Note 3)
ICC3	Supply Current (RESET, 2.7V)
	80L186EA-13			34	mA	(Note 3)
	80L186EA-8			20	mA	(Note 3)
IID5	Supply Current Idle (5.5V)
	80L186EA-13			46	mA
	80L186EA-8			28	mA
IID5	Supply Current Idle (2.7V)
	80L186EA-13			24	mA
	80L186EA-8			14	mA
IPD5	Supply Current Powerdown (5.5V)
	80L186EA-13			100	mA
	80L186EA-8			100	mA
IPD3	Supply Current Powerdown (2.7V)
	80L186EA-13			50	mA
	80L186EA-8			50	mA
COUT	Output Pin Capacitance		0	15	pF	TF e 1 MHz (Note 4)
CIN	Input Pin Capacitance		0	15	pF	TF e 1 MHz

NOTES:

1.RD/QSMD, UCS, LCS, MCS0, MCS1, LOCK and TEST have internal pullups that are only activated during RESET. Loading these pins above IOL e b275 mA will cause the processor to enter alternate modes of operation.

2.Output pins are floated using HOLD or ONCE Mode.

3.Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test Conditions, and with the device in RESET (RESIN held low).

4.Output capacitance is the capacitive load of a floating output pin.

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