Contents
BIT HIGH-INTEGRATION Embedded Processors
Contentspage
C186EA/80C188EA Block Diagram
Bus Interface Unit
Introduction
80C186EA Core Architecture
Clock Generator
Interrupt Control Unit
Timer/Counter Unit
80C186EA Peripheral Architecture
Crystal Connection Clock Connection
Peripheral Control Block Registers
Chip-Select Unit
Power Management
DMA Control Unit
Refresh Control Unit
Differences Between the 80C186XL and the 80C186EA
Plcc
Package Information
Pin Descriptions
QFP Eiaj
RWH
Resin
Clkin
Oscout
Resout
Rfsh
ALE/QS0
BHE
RD/QSMD
Srdy
WR/QS1
Ardy
DEN
MCS2
MCS1/ERROR
MCS0/PEREQ
MCS3/NCS
80C186EA Pinout
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Lead Plcc Pinout Diagram
Plcc Package Location with Pin Names
QFP Eiaj Pin Names with Package Location
Quad Flat Pack Eiaj Pinout Diagram
QFP Eiaj Package Location with Pin Names
Hlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT
Sqfp Pin Functions with Package Location
Sqfp Pin Locations with Pin Names
UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1
Package Thermal Specifications
400 600 800 1000 CA Plcc
CA QFP 60.5 CA Sqfp
Absolute Maximum Ratings
Electrical Specifications
Voltage on Other Pins with Respect
Recommended Connections
DC Specifications 80C186EA/80C188EA
RD/QSMD, UCS, LCS, MCS0/PEREQ
DC Specifications 80L186EA/80L188EA
RD/QSMD, UCS, LCS, MCS0
And/or higher temperature will increase delay time
Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c f
Pdtmr PIN Delay Calculation
ICC Versus Frequency and Voltage
AC Specifications
AC Characteristics-80C186EA25/80C186EA20/80C186EA13
TEST, NMI, INT30 T10IN, Ardy
HOLD, PEREQ, Error
Synchronous Inputs
SRDY, DRQ10
MCS30, LCS, UCS
AC Characteristics-80L186EA13/80L186EA8
ALE, Lock
LOCK, RESOUT, Hlda T0OUT, T1OUT
TEST, NMI, INT30, T10IN, Ardy
AD150 AD70, ARDY, SRDY, DRQ10
Relative Timings
AC Test Conditions
AC Timing Waveforms
Output Delay and Float Waveform
Relative Signal Waveform
Reset
Derating Curves
Powerup Reset Waveforms
Warm Reset Waveforms
BUS Cycle Waveforms
Read, Fetch and Refresh Cycle Waveform
Write Cycle Waveform
Halt Cycle Waveform
Inta Cycle Waveform
HOLD/HLDA Waveform
Dram Refresh Cycle During Hold Acknowledge
Ready Waveform
80C186EA/80C188EA Execution Timings
Instruction SET Summary
Data Transfer
Instruction SET Summary
Arithmetic
Logic
String Manipulation
Within seg adding immed to SP
010 DX 010 DL
100 SP
101 BP 101 CH 110 SI 110 DH 111 DI 111 BH
Revision History
Errata