Intel 80L186EA, 80L188EA, 80C188EA TEST, NMI, INT30, T10IN, Ardy, AD150 AD70, ARDY, SRDY, DRQ10

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80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS

AC Characteristics—80L186EA13/80L186EA8

Symbol

 

 

 

Parameter

Min

Max

Min

Max

Units

Notes

 

 

 

 

 

 

 

 

 

 

 

SYNCHRONOUS INPUTS

13 MHz

8 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

TCHIS

 

TEST, NMI, INT3:0, T1:0IN, ARDY

22

 

22

 

ns

1, 9

 

 

 

 

 

 

 

 

 

 

 

TCHIH

 

TEST, NMI, INT3:0, T1:0IN, ARDY

3

 

3

 

ns

1, 9

TCLIS

 

AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0

22

 

22

 

ns

1, 10

TCLIH

 

AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0

3

 

3

 

ns

1, 10

TCLIS

 

HOLD

22

 

22

 

ns

1, 9

TCLIH

 

HOLD

3

 

3

 

ns

1, 9

 

 

 

 

 

 

 

 

 

 

TCLIS

 

RESIN (to CLKIN)

22

 

22

 

ns

1, 9

 

 

 

 

 

 

 

 

 

 

TCLIH

 

RESIN (from CLKIN)

3

 

3

 

ns

1, 9

NOTES:

1.See AC Timing Waveforms, for waveforms and definition.

2.Measured at VIH for high time, VIL for low time.

3.Only required to guarantee ICC. Maximum limits are bounded by TC, TCH and TCL.

4.Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5.Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6.See Figure 14 for rise and fall times.

7.TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8.TCHOV2 applies to RD and WR only after a HOLD release.

9.Setup and Hold are required to guarantee recognition.

10.Setup and Hold are required for proper operation.

11.TCHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release.

12.Pin names in parentheses apply to the 80C188EA/80L188EA.

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Contents BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Introduction 80C186EA Core ArchitectureBus Interface Unit Clock GeneratorTimer/Counter Unit 80C186EA Peripheral ArchitectureInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers Power Management DMA Control UnitChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Package Information Pin DescriptionsPlcc QFP EiajRWH Clkin OscoutResin ResoutALE/QS0 BHERfsh RD/QSMDWR/QS1 ArdySrdy DENMCS1/ERROR MCS0/PEREQMCS2 MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesSqfp Pin Functions with Package Location Sqfp Pin Locations with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1400 600 800 1000 CA Plcc Package Thermal SpecificationsCA QFP 60.5 CA Sqfp Electrical Specifications Voltage on Other Pins with RespectAbsolute Maximum Ratings Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c f Pdtmr PIN Delay CalculationAnd/or higher temperature will increase delay time ICC Versus Frequency and Voltage AC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13HOLD, PEREQ, Error Synchronous InputsTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10AC Characteristics-80L186EA13/80L186EA8 ALE, LockMCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 100 SP 010 DX 010 DL101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Revision History Errata