Ampro Corporation 700 manual DRQ0, DACK5, DRQ5, DACK6, DRQ6, DACK7, DRQ7, Master

Page 38

Chapter 3

 

 

Hardware

 

 

 

 

 

 

 

30

(D9)

DRQ0

DMA Request 0 – Used by I/O resources to request DMA service.

 

 

 

 

 

Must be held high until associated DACK0 line is active.

 

 

31

(D10)

DACK5*

DMA Acknowledge 5 – Used by DMA controller to select the I/O

 

 

 

 

 

resource requesting the bus, or to request ownership of the bus as a bus

 

 

 

 

 

master device. Can also be used by the ISA bus master to gain control

 

 

 

 

 

of the bus from the DMA controller.

 

 

32

(D11)

DRQ5

DMA Request 5 – Used by I/O resources to request DMA service.

 

 

 

 

 

Must be held high until associated DACK5 line is active.

 

 

33

(D12)

DACK6*

DMA Acknowledge 6 – Used by DMA controller to select the I/O

 

 

 

 

 

resource requesting the bus, or to request ownership of the bus as a bus

 

 

 

 

 

master device. Can also be used by the ISA bus master to gain control

 

 

 

 

 

of the bus from the DMA controller.

 

 

34

(D13)

DRQ6

DMA Request 6 – Used by I/O resources to request DMA service.

 

 

 

 

 

Must be held high until associated DACK6 line is active.

 

 

35

(D14)

DACK7*

DMA Acknowledge 7 – Used by DMA controller to select the I/O

 

 

 

 

 

resource requesting the bus, or to request ownership of the bus as a bus

 

 

 

 

 

master device. Can also be used by the ISA bus master to gain control

 

 

 

 

 

of the bus from the DMA controller.

 

 

36

(D15)

DRQ7

DMA Request 7 – Used by I/O resources to request DMA service.

 

 

 

 

 

Must be held high until associated DACK7 line is active.

 

 

37

(D16)

+5V

+5 volt power ±10%

 

 

38

(D17)

MASTER*

Bus Master Assert – This signal is used by an ISA board along with a

 

 

 

 

 

DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK

 

 

 

 

 

a device can pull -MASTER low which will allow it to control the

 

 

 

 

 

system address, data, and control lines. After -MASTER is low, the

 

 

 

 

 

device should wait one CLK period before driving the address and data

 

 

 

 

 

lines, and two clock periods before issuing a read or write command.

 

 

39

(D18)

GND

Ground

 

 

40

(D19)

GND

Ground

 

 

 

 

 

 

 

Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.

32

Reference Manual

ReadyBoard 700

Image 38
Contents ReadyBoard Single Board Computer Reference Manual Audience Assumptions Revision HistoryContents Appendix a List of Tables Reference Manual ReadyBoard Reference Material SpecificationsPurpose of this Manual Other ReadyBoard Products Related Ampro ProductsReadyBoard 700 Support Products Other Ampro ProductsChapter Reference Manual ReadyBoard Product Overview Epic ArchitectureBoard Features Product DescriptionChapter Chapter Block Diagram ATACPU Major Integrated Circuits ICsChip Type Mfg Model Description Function VIAJack # Signal/Device Description Connector DefinitionsSwitch Definition Component DescriptionAll illustrations Lvds J7Additional Components IllustrationsIndicator Definition Power/IDE LED DefinitionsJumper # Installed Removed Jumper DefinitionsJumper, Switch, and LED Locations Top view Power Specifications SpecificationsPhysical Specifications Environmental SpecificationsMechanical Specifications Thermal/Cooling RequirementsReadyBoard 700 Side view Chapter Hardware OverviewSdram Memory DIMM1 CPU U4Memory Flash MemoryInterrupt Channel Assignments Memory MapAddress hex Subsystem Address MapBase Address Function CF8-CFFPin # Signal Input Description Output PC/104-Plus Interface J12CLK2 REQ0GNT1 PerrIntd REQ2CLK0 IntaGNT2 IDSEL1REQ1 CLK3GNT0 IDSEL2IDSEL3 CLK1Pin # Signal Description J13 Row a PC/104 Interface J13 A/B, J14 C/DPin # Signal Descriptions J13 Row B Pin # Signal Descriptions J14 Row C Pin # Signal Descriptions J14 Row D DRQ5 DRQ0DACK5 DACK6Pin # Signal Description IDE Interface J22Pdiordy PdiowPdior PdcselCompactFlash Adapter J23 SDD11 CFD2CFD1 SDD12Floppy/Parallel Interface J20 Autofdx SlctinStep DrvenoSerial Interfaces J5A/B, J3A/B RS485 Serial Port ImplementationSerial a Interface J5A/B Serial B Interface J3A/B CTS4 DTR4Secondary USB2 and USB3 J21A/B USB Interfaces J15A/B, J21A/BPrimary USB0 and USB1 J15A/B Digital Ground Ethernet Interfaces J10, J11Pin # Audio Interface J19 Video Interfaces J8, J9, J7 CRT Interface J8LCD Interface J9 Pin # Signal Description Line Channel Lvds Interface J7Utility Interface J18 Reset Switch SW1Miscellaneous Keyboard/Mouse Interface J16Real Time Clock RTC Oops! Jumper Bios RecoveryInfrared IrDA Port J17 IrtxSerial Console User Gpio Signals J2Temperature Monitoring Watchdog Timer Serial Console SetupPower-On Interface J6 Power Interfaces J4, J6Power In Interface J4 VccsbReference Manual ReadyBoard Accessing Bios Setup VGA Display IntroductionAccessing Bios Setup Serial Console Bios Setup Menu Item/TopicBios Menus Bios Setup Opening ScreenDrive Assignments Bios Configuration ScreenDate & Time # of Floppy Drives Bios Settings Boot OrderDrive and Boot Options Memory Keyboard and Mouse ConfigurationUser Interface Power Management Advanced featuresChapter Bios Setup On-Board Serial Ports On-Board LPT PortOn-Board Controllers On-Board VideoType LCD ResolutionPanel Type 640 x 480 x 18 TFT 640 x 480 x 18 bitChapter Bios Setup Chapter Bios Setup Chapter Bios Setup Converting the Splash Screen File Splash Screen CustomizationSplash Screen Image Requirements \splashconvert convert.idf Reference Manual ReadyBoard Appendix a Technical Support Method Contact InformationAppendix a Appendix B LAN Boot Option PXE Boot Agent Bios Setup Accessing PXE Boot Agent Bios SetupTCP/IP Configuration PXE Boot Agent Setup ScreenPXE Configuration NetWare Configuration RPL ConfigurationCD-ROM LEDRTC PostWatchdog timer WDT Table notes Reference Manual ReadyBoard