Ampro Corporation 700 manual Video Interfaces J8, J9, J7, CRT Interface J8

Page 52

Chapter 3

Hardware

Video Interfaces (J8, J9, J7)

The VT8606 chip provides the graphics control and video signals to the traditional glass CRT monitors and the LCD and LVDS flat panel displays. The chip features are listed below:

CRT features:

Supports a max resolution of 1600 x 1200 with video frame buffer set at 8MB

Supports a maximum allowable video frame buffer size of 32MB UMA (Unified Memory Architecture)

AGP 4x graphics (always enabled)

Compliant with Rev 2.0 of AGP Interface

Flat Panel features:

Supports (3.3V, 5V, or 12V) output to both DSTN and TFT flat panels through a 36-bit interface

Supports TFT panel sizes from VGA (320x480) up to SXGA+ and UXGA+ (1400x1050).

Supports LCD VGA and SVGA panels with 9-, 12-, 18-bit interface (1 Pixel/Clock)

Supports UXGA and SXGA active matrix panels with 1x24-bit interface (2 Pixels/Clock)

Supports 1 or 2 channel LVDS outputs

CRT Interface (J8)

Table 3-20. CRT Interface Pin/Signal Descriptions (J8)

Pin #

Signal

Description

1

RED

Red – This is the Red analog output signal to the CRT.

 

 

 

2

GREEN

Green – This is the Green analog output signal to the CRT.

 

 

 

3

BLUE

Blue – This is the Blue analog output signal to the CRT.

 

 

 

4

NC

Not connected

 

 

 

5

GND

Digital Ground

6

GND

Digital Ground

7

GND

Digital Ground

8

GND

Digital Ground

9

NC

Not connected

 

 

 

10

GND

Digital Ground

11

NC

Not connected

 

 

 

12

DDDA

Display Data Channel Data – This signal line provides information to the CPU

 

 

through the Northbridge about the monitor type, brand, and model. This is part

 

 

of the Plug and Play standard developed by the VESA trade association.

13

HSYNC

Horizontal Sync – This signal is used for the digital horizontal sync output to

 

 

the CRT.

14

VSYNC

Vertical Sync – This signal is used for the digital vertical sync output to the CRT.

 

 

 

15

DDCLK

Display Data Channel Clock – This signal line provides the data clock signal to

 

 

the CPU through the Northbridge from the monitor. This is part of the Plug and

 

 

Play standard developed by the VESA trade association.

Notes: The shaded area denotes power or ground.

46

Reference Manual

ReadyBoard 700

Image 52
Contents ReadyBoard Single Board Computer Reference Manual Audience Assumptions Revision HistoryContents Appendix a List of Tables Reference Manual ReadyBoard Purpose of this Manual SpecificationsReference Material Related Ampro Products ReadyBoard 700 Support ProductsOther ReadyBoard Products Other Ampro ProductsChapter Reference Manual ReadyBoard Product Overview Epic ArchitectureBoard Features Product DescriptionChapter Chapter Block Diagram ATAMajor Integrated Circuits ICs Chip Type Mfg Model Description FunctionCPU VIAConnector Definitions Switch DefinitionJack # Signal/Device Description Component DescriptionAll illustrations Lvds J7Additional Components IllustrationsPower/IDE LED Definitions Jumper # Installed RemovedIndicator Definition Jumper DefinitionsJumper, Switch, and LED Locations Top view Specifications Physical SpecificationsPower Specifications Environmental SpecificationsMechanical Specifications Thermal/Cooling RequirementsReadyBoard 700 Side view Chapter Hardware OverviewCPU U4 MemorySdram Memory DIMM1 Flash MemoryInterrupt Channel Assignments Memory MapAddress Map Base Address FunctionAddress hex Subsystem CF8-CFFPin # Signal Input Description Output PC/104-Plus Interface J12REQ0 GNT1CLK2 PerrREQ2 CLK0Intd IntaIDSEL1 REQ1GNT2 CLK3IDSEL2 IDSEL3GNT0 CLK1Pin # Signal Description J13 Row a PC/104 Interface J13 A/B, J14 C/DPin # Signal Descriptions J13 Row B Pin # Signal Descriptions J14 Row C Pin # Signal Descriptions J14 Row D DRQ0 DACK5DRQ5 DACK6Pin # Signal Description IDE Interface J22Pdiow PdiorPdiordy PdcselCompactFlash Adapter J23 CFD2 CFD1SDD11 SDD12Floppy/Parallel Interface J20 Slctin StepAutofdx DrvenoSerial Interfaces J5A/B, J3A/B RS485 Serial Port ImplementationSerial a Interface J5A/B Serial B Interface J3A/B CTS4 DTR4 Primary USB0 and USB1 J15A/B USB Interfaces J15A/B, J21A/B Secondary USB2 and USB3 J21A/B Pin # Ethernet Interfaces J10, J11Digital Ground Audio Interface J19 Video Interfaces J8, J9, J7 CRT Interface J8LCD Interface J9 Pin # Signal Description Line Channel Lvds Interface J7Reset Switch SW1 MiscellaneousUtility Interface J18 Keyboard/Mouse Interface J16Oops! Jumper Bios Recovery Infrared IrDA Port J17Real Time Clock RTC IrtxTemperature Monitoring User Gpio Signals J2Serial Console Watchdog Timer Serial Console SetupPower Interfaces J4, J6 Power In Interface J4Power-On Interface J6 VccsbReference Manual ReadyBoard Accessing Bios Setup VGA Display IntroductionAccessing Bios Setup Serial Console Bios Setup Menu Item/TopicBios Menus Bios Setup Opening ScreenDate & Time Bios Configuration ScreenDrive Assignments # of Floppy Drives Bios Settings Boot OrderDrive and Boot Options User Interface Keyboard and Mouse ConfigurationMemory Power Management Advanced featuresChapter Bios Setup On-Board Serial Ports On-Board LPT PortOn-Board Controllers On-Board VideoLCD Resolution Panel Type 640 x 480 x 18 TFTType 640 x 480 x 18 bitChapter Bios Setup Chapter Bios Setup Chapter Bios Setup Splash Screen Image Requirements Splash Screen CustomizationConverting the Splash Screen File \splashconvert convert.idf Reference Manual ReadyBoard Appendix a Technical Support Method Contact InformationAppendix a Appendix B LAN Boot Option PXE Boot Agent Bios Setup Accessing PXE Boot Agent Bios SetupPXE Configuration PXE Boot Agent Setup ScreenTCP/IP Configuration NetWare Configuration RPL ConfigurationCD-ROM LEDRTC PostWatchdog timer WDT Table notes Reference Manual ReadyBoard