Ampro Corporation 700 manual Power Management, Advanced features

Page 68

Chapter 4

BIOS Setup

Memory Hole – [Disabled], [1MB], or [2MB]

This field specifies the size of an optional memory hole, below 16MB. Access to the memory addresses inside the memory hole region are forwarded to the PC/104 bus, where memory mapped PC/104 devices have access.

Shadow D000-D3FF – [Disabled] or [Enabled]

These Shadow fields specify if BIOS option ROMs in the indicated segments should be shadowed to RAM. Shadowing option ROMs can potentially speed up the operation of the system. The indicated segments are only for option ROMs present on add-on PC/104 and PC/104-Plus cards.

Shadow D400-D7FF– [Disabled] or [Enabled]

Shadow D800-DBFF – [Disabled] or [Enabled]

Shadow DC00-DFFF – [Disabled] or [Enabled]

DRAM

DRAM Clock Frequency – [SPD] or [PC100] This field specifies the DRAM clock frequency.

If this field is set to SPD (Serial Presence Detect), then the DRAM clock is set using the information read from the SPD(s) on the SDRAM module(s).

If this field is set to PC100, the clock will override the SDRAM SPD information and force the SDRAM clock to 100MHz.

NOTE

The SDRAM clock frequency can never be set higher than

 

the CPU’s Front Side Bus (FSB) clock frequency,

 

regardless of the SPD or PC100 setting.

 

 

DRAM CAS Latency – [SPD], [CAS 3], or [CAS 2]

This field specifies the DRAM CAS (Column Address Strobe) Latency

If this field is set to SPD, then the DRAM CAS latency is set using the information read from the SPD(s) on the DRAM module(s).

If this field is set to CAS 2 or CAS 3, the setting will override the DRAM SPD information and force the DRAM CAS latency to the specified value.

Power Management

ACPI – [Disabled] or [Enabled]

If this field is set to [Enabled], the Advanced Configuration and Power Interface API is turned on.

APM – [Disabled] or [Enabled]

If this field is set to [Enabled], the Advanced Power Management API is turned on.

Advanced features

Post Memory Manager – [Disabled] or [Enabled]

If this field is set to [Enabled], the Post Memory Manger API is turned on. The Post Memory Manger can be used by BIOS option ROMs to allocate memory in a well defined way.

CPU Serial Number – [Disabled] or [Enabled]

If this field is set to [Enabled], the internal serial number in the Intel CPU is accessible by the Operating System and/or Applications that can make use of this information..

62

Reference Manual

ReadyBoard 700

Image 68
Contents ReadyBoard Single Board Computer Reference Manual Audience Assumptions Revision HistoryContents Appendix a List of Tables Reference Manual ReadyBoard Reference Material SpecificationsPurpose of this Manual Related Ampro Products ReadyBoard 700 Support ProductsOther ReadyBoard Products Other Ampro ProductsChapter Reference Manual ReadyBoard Product Overview Epic ArchitectureBoard Features Product DescriptionChapter Chapter Block Diagram ATAMajor Integrated Circuits ICs Chip Type Mfg Model Description FunctionCPU VIAConnector Definitions Switch DefinitionJack # Signal/Device Description Component DescriptionAll illustrations Lvds J7Additional Components IllustrationsPower/IDE LED Definitions Jumper # Installed RemovedIndicator Definition Jumper DefinitionsJumper, Switch, and LED Locations Top view Specifications Physical SpecificationsPower Specifications Environmental SpecificationsMechanical Specifications Thermal/Cooling RequirementsReadyBoard 700 Side view Chapter Hardware OverviewCPU U4 MemorySdram Memory DIMM1 Flash MemoryInterrupt Channel Assignments Memory MapAddress Map Base Address FunctionAddress hex Subsystem CF8-CFFPin # Signal Input Description Output PC/104-Plus Interface J12REQ0 GNT1CLK2 PerrREQ2 CLK0Intd IntaIDSEL1 REQ1GNT2 CLK3IDSEL2 IDSEL3GNT0 CLK1Pin # Signal Description J13 Row a PC/104 Interface J13 A/B, J14 C/DPin # Signal Descriptions J13 Row B Pin # Signal Descriptions J14 Row C Pin # Signal Descriptions J14 Row D DRQ0 DACK5DRQ5 DACK6Pin # Signal Description IDE Interface J22Pdiow PdiorPdiordy PdcselCompactFlash Adapter J23 CFD2 CFD1SDD11 SDD12Floppy/Parallel Interface J20 Slctin StepAutofdx DrvenoSerial Interfaces J5A/B, J3A/B RS485 Serial Port ImplementationSerial a Interface J5A/B Serial B Interface J3A/B CTS4 DTR4Secondary USB2 and USB3 J21A/B USB Interfaces J15A/B, J21A/BPrimary USB0 and USB1 J15A/B Digital Ground Ethernet Interfaces J10, J11Pin # Audio Interface J19 Video Interfaces J8, J9, J7 CRT Interface J8LCD Interface J9 Pin # Signal Description Line Channel Lvds Interface J7Reset Switch SW1 MiscellaneousUtility Interface J18 Keyboard/Mouse Interface J16Oops! Jumper Bios Recovery Infrared IrDA Port J17Real Time Clock RTC IrtxSerial Console User Gpio Signals J2Temperature Monitoring Watchdog Timer Serial Console SetupPower Interfaces J4, J6 Power In Interface J4Power-On Interface J6 VccsbReference Manual ReadyBoard Accessing Bios Setup VGA Display IntroductionAccessing Bios Setup Serial Console Bios Setup Menu Item/TopicBios Menus Bios Setup Opening ScreenDrive Assignments Bios Configuration ScreenDate & Time # of Floppy Drives Bios Settings Boot OrderDrive and Boot Options Memory Keyboard and Mouse ConfigurationUser Interface Power Management Advanced featuresChapter Bios Setup On-Board Serial Ports On-Board LPT PortOn-Board Controllers On-Board VideoLCD Resolution Panel Type 640 x 480 x 18 TFTType 640 x 480 x 18 bitChapter Bios Setup Chapter Bios Setup Chapter Bios Setup Converting the Splash Screen File Splash Screen CustomizationSplash Screen Image Requirements \splashconvert convert.idf Reference Manual ReadyBoard Appendix a Technical Support Method Contact InformationAppendix a Appendix B LAN Boot Option PXE Boot Agent Bios Setup Accessing PXE Boot Agent Bios SetupTCP/IP Configuration PXE Boot Agent Setup ScreenPXE Configuration NetWare Configuration RPL ConfigurationCD-ROM LEDRTC PostWatchdog timer WDT Table notes Reference Manual ReadyBoard