Ampro Corporation 700 manual Ethernet Interfaces J10, J11, Pin #, Digital Ground

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Chapter 3

Hardware

Ethernet Interfaces (J10, J11)

The Ethernet solution is provided by two Intel 82551ER PCI controller chips, which consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82551ER to perform high-speed data transfers over the PCI bus. The 82551ER bus master capabilities enable the component to process high-level commands and perform multiple operations, thereby off-loading communication tasks from the system CPU.

Backward software compatible to the 82559, 82558, and 82557

Chained memory structure

Full duplex or half-duplex support

Full duplex support at 10Mbps and 100Mbps

In half-duplex mode, performance is enhanced by a proprietary collision reduction mechanism.

IEEE 802.3 10BaseT/100BaseT compatible physical layer to wire transformer

2 LED support for each port (speed, and link and activity are shared)

Data transmission with minimum interframe spacing (IFS).

IEEE 802.3u Auto-Negotiation support

3kB transmit and 3kB receive FIFOs (helps prevent data underflow and overflow)

IEEE 802.3x 100BASE-TX flow control support

Improved dynamic transmit chaining with multiple priorities transmit queues

Each Ethernet port has a RJ-45 connector and the related magnetics integrated on the board.

Each Ethernet port controller connected to Primary PCI bus

Tables 3-17 and 3-18 describe the pin-outs and signals of two Ethernet ports 1 and 2, respectively.

Table 3-17. Ethernet Port 1 Pin/Signal Descriptions (J10)

Pin #

GND

Digital Ground

1

TX1+

Analog Twisted Pair Ethernet Transmit Differential Pair. These pins transmit

 

 

 

the serial bit stream for transmission on the Unshielded Twisted Pair Cable

3

TX1-

(UTP). These signals interface directly with an isolation transformer.

 

 

 

 

 

 

 

4

RX1+

Analog Twisted Pair Ethernet Receive Differential Pair. These pins receive the

 

 

 

serial bit stream from the isolation transformer.

6

RX1-

 

 

 

 

 

9

ACT

Link/Activity signal indicates a Link is established or Activity is occurring

 

 

 

 

11

SPEED

Speed signal for 10BaseT or 100BaseT transfer rate

 

 

 

 

2, 7, 8

 

NC

Not connected

 

 

 

5, 13, 14

GND

Grounded (goes to ground through 0.1∝ capacitor)

10, 12

 

+3VSB

+3V for plus side of LEDs. See Table 2-6.

 

 

 

 

Notes: The shaded area denotes power or ground.

44

Reference Manual

ReadyBoard 700

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Contents ReadyBoard Single Board Computer Reference Manual Audience Assumptions Revision HistoryContents Appendix a List of Tables Reference Manual ReadyBoard Reference Material SpecificationsPurpose of this Manual Other ReadyBoard Products Related Ampro ProductsReadyBoard 700 Support Products Other Ampro ProductsChapter Reference Manual ReadyBoard Product Overview Epic ArchitectureBoard Features Product DescriptionChapter Chapter Block Diagram ATACPU Major Integrated Circuits ICsChip Type Mfg Model Description Function VIAJack # Signal/Device Description Connector DefinitionsSwitch Definition Component DescriptionAll illustrations Lvds J7Additional Components IllustrationsIndicator Definition Power/IDE LED DefinitionsJumper # Installed Removed Jumper DefinitionsJumper, Switch, and LED Locations Top view Power Specifications SpecificationsPhysical Specifications Environmental SpecificationsMechanical Specifications Thermal/Cooling RequirementsReadyBoard 700 Side view Chapter Hardware OverviewSdram Memory DIMM1 CPU U4Memory Flash MemoryInterrupt Channel Assignments Memory MapAddress hex Subsystem Address MapBase Address Function CF8-CFFPin # Signal Input Description Output PC/104-Plus Interface J12CLK2 REQ0GNT1 PerrIntd REQ2CLK0 IntaGNT2 IDSEL1REQ1 CLK3GNT0 IDSEL2IDSEL3 CLK1Pin # Signal Description J13 Row a PC/104 Interface J13 A/B, J14 C/DPin # Signal Descriptions J13 Row B Pin # Signal Descriptions J14 Row C Pin # Signal Descriptions J14 Row D DRQ5 DRQ0DACK5 DACK6Pin # Signal Description IDE Interface J22Pdiordy PdiowPdior PdcselCompactFlash Adapter J23 SDD11 CFD2CFD1 SDD12Floppy/Parallel Interface J20 Autofdx SlctinStep DrvenoSerial Interfaces J5A/B, J3A/B RS485 Serial Port ImplementationSerial a Interface J5A/B Serial B Interface J3A/B CTS4 DTR4Secondary USB2 and USB3 J21A/B USB Interfaces J15A/B, J21A/BPrimary USB0 and USB1 J15A/B Digital Ground Ethernet Interfaces J10, J11Pin # Audio Interface J19 Video Interfaces J8, J9, J7 CRT Interface J8LCD Interface J9 Pin # Signal Description Line Channel Lvds Interface J7Utility Interface J18 Reset Switch SW1Miscellaneous Keyboard/Mouse Interface J16Real Time Clock RTC Oops! Jumper Bios RecoveryInfrared IrDA Port J17 IrtxSerial Console User Gpio Signals J2Temperature Monitoring Watchdog Timer Serial Console SetupPower-On Interface J6 Power Interfaces J4, J6Power In Interface J4 VccsbReference Manual ReadyBoard Accessing Bios Setup VGA Display IntroductionAccessing Bios Setup Serial Console Bios Setup Menu Item/TopicBios Menus Bios Setup Opening ScreenDrive Assignments Bios Configuration ScreenDate & Time # of Floppy Drives Bios Settings Boot OrderDrive and Boot Options Memory Keyboard and Mouse ConfigurationUser Interface Power Management Advanced featuresChapter Bios Setup On-Board Serial Ports On-Board LPT PortOn-Board Controllers On-Board VideoType LCD ResolutionPanel Type 640 x 480 x 18 TFT 640 x 480 x 18 bitChapter Bios Setup Chapter Bios Setup Chapter Bios Setup Converting the Splash Screen File Splash Screen CustomizationSplash Screen Image Requirements \splashconvert convert.idf Reference Manual ReadyBoard Appendix a Technical Support Method Contact InformationAppendix a Appendix B LAN Boot Option PXE Boot Agent Bios Setup Accessing PXE Boot Agent Bios SetupTCP/IP Configuration PXE Boot Agent Setup ScreenPXE Configuration NetWare Configuration RPL ConfigurationCD-ROM LEDRTC PostWatchdog timer WDT Table notes Reference Manual ReadyBoard